Reset ULP bit after stop (STM32L1)

[Mark Ruys]

Posted on May 14, 2018 at 21:30

After I upgraded my application from mbed 5.4.7 to 5.7.7, my comparator is unreliable after a STOP. Basically, this is how the MCU is put into sleep (from

https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c

:(

HAL_PWREx_EnableUltraLowPower();

HAL_PWREx_EnableFastWakeUp();...HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);...while ( ! LL_PWR_IsActiveFlag_VREFINTRDY() ) {};

I assume this has to do with V_REFINT being unstable after resuming the sleep condition.

All works good again when I add a call to 

HAL_PWREx_DisableUltraLowPower()

after wake up. Although now I'm happy to have the comparator to work stable again after a stop, disabling the ULP bit in the PWR_CR register doesn't make sense to me when I read the datasheets. What am I missing here?

MCU is a STM32L151 (part of a Multitech xDot).

#stm32l1 #wake-up-from-stop-mode

[dz huang]

Posted on May 31, 2018 at 08:56

I using STM32L071RBT6, encounter similar issues, when I set ULP bit by '

HAL_PWREx_EnableUltraLowPower()', the systemtick (using TIM2 as time base) become very slow.

when I clear ULP bit by '

HAL_PWREx_DisableUltraLowPower()

', the systemtick back to normal.

I am also very confusing.

[dz huang]

Posted on June 01, 2018 at 10:12

My issue fixed by clear LPSDSR bit in PWR->CR after wakup from STOP mode. you can try

CLEAR_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR));

[Mark Ruys]

Posted on June 19, 2018 at 09:50

alexhuang

, it seems your issue is something else. I'vetested

CLEAR_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR))

but it didn't help. What didworkwas to call this function after recovering from stop mode:

/**

* @brief Disables the Ultra Low Power mode

* @retval None

*/

void HAL_PWREx_DisableUltraLowPower(void)

{

/* Disable the Ultra Low Power mode */

*(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;

}