2015-08-07 09:17 PM
I'm working with the Nucleo F446RE, and the project that I created using the STM32 Workbench as well as all the standard library files include the stm32f4xx.h file rather than the stm32f446xx.h
I noticed that the GPIO registers do not match the ones in the reference manual for theSTM32F446RET6, which shows a BSRR register rather than the BSRRL and BSRRH. Why is the STM32 System Workbench IDE including this file if it doesn't have the correct descriptions, or am I doing something wrong?/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
2015-08-07 09:38 PM
It's a 32-bit register that can be accessed via two 16-bit halves. The lower half setting, the upper half clearing. A lot of people find the split version more convenient, if you want to deal with it as a 32-bit entity, cast the pointer appropriately.
They could perhaps have used an unnamed union, but that makes some C compilers choke.