2020-05-02 01:51 PM
The doc and SVD file don't have a reg at offset 0x44 (GTZC_TZSC_MPCWM3BNSR).
Since GTZC_TZSC_MPCWM3ANSR @0x40 exists, via symmetry I would expect B also at 0x44.
The doc does say this:
GTZC_TZSC external memory x non-secure watermark register 1
(GTZC_TZSC_MPCWMxANSR)
Address offset: 0x030 + 0x008 * (x-1), (x = 1 to 3)
and
GTZC_TZSC external memory x non-secure watermark register 2
(GTZC_TZSC_MPCWMxBNSR)
Address offset: 0x034 + 0x008 * (x-1), (x = 1 to 2)
In the debugger... it looks like its there... Here I set x=(1..3) for A&B
(gdb) set *0x50032430=0x11223344
(gdb) set *0x50032434=0x55667788
(gdb) set *0x50032438=0x44332211
(gdb) set *0x5003243c=0x88776655
(gdb) set *0x50032440=0xaabbccdd
(gdb) set *0x50032444=0xffeeddcc
(gdb) x/32x 0x50032400
0x50032400: 0x00000000 0x00000000 0x00000000 0x00000000
0x50032410: 0x00000000 0x00000000 0x00000000 0x00000000
0x50032420: 0x00000000 0x00000000 0x00000000 0x00000000
0x50032430: 0x01220344 0x00780788 0x04330211 0x01ab0655
0x50032440: 0x032304dd 0x023405cc 0x00000000 0x00000000
0x50032450: 0x00000000 0x00000000 0x00000000 0x00000000
0x50032460: 0x00000000 0x00000000 0x00000000 0x00000000
0x50032470: 0x00000000 0x00000000 0x00000000 0x00000000
tnx
Hedley
2020-07-29 07:53 AM
2020-07-29 10:32 AM
Hi Imen,
1.1
Tnx
Hedley
2020-07-30 03:56 AM
Hi Hedley,
I did verify and today we have a more advansed version (v1.4) for the STM32L5 svd files with more fixes if you are interested.
Nevertheless regarding the point you raised, I can see your confusing about expecting via symmetry a B register at 0x44 like for GTZC_TZSC_MPCWM3ANSR.
In our SVD deliveries we have to be aligned with RM (RM0438) which according to description GTZC_TZSC is limited at @0x40.
I am going to raise this point internally basing on your Debug observation and hopefully come back to you soon with an answer.
Thank you for your feedbacks!
-Imen