I can build a “timer” using a counter with “decoder” circuitry to create an output signal at a specific time after starting the counter...
Alternately, after each clock to the counter, the counters output value could be compared to some register value... and if they matched... create the output signal.
So, as described, this counter would have only one output signal.
In looking at the Reference Manual RM0399 Figure 323 on page 1505 I see that...
Timer A has two outputs... HRTM_CHA1 and HTRM_CHA2.
Ditto for Timers B through E.
The Question-1: What are these “Channels” and how do they relate to their respective timers output...
(as, again, timers I’ve worked with generally have one output... or maybe the output and the compliment of the output.)
A wild guess would be that each “timer” can create an output signal at time delay 1 and another at time delay 2...
or what?
Question-2: Section 39.3.1 second paragraph “set/reset events” are mentioned...
In this context does “set/reset event” mean what happens when the timer reaches its designated count and outputs a signal indicating such... either a pulse or level change or whatever?
(My confusion comes from the idea that when the timer reaches its designated count it may simply remove the clock from its input and not be set or reset until later.)
Thanks for any help.
