Question about FSMC of STM32F103VE?

e_zhui · ‎2008-09-27

Posted on September 28, 2008 at 03:35

e_zhui · ‎2011-05-17

Posted on May 17, 2011 at 12:46

Hello,

I want to use STM32F103VE to access my two devices which both have a sram-like bus, 8-bit data line and 1-bit address line, #rd/#wr/#cs.

But STM32F103VE has only ONE NOR/PSRAM bank bank and its address bus comes with A16~A23/A25. So I am not very sure if STM32F103VE can access my devices?Or do I need to add some glue logics?

Regards,

jj · ‎2011-05-17

Posted on May 17, 2011 at 12:46

Don't have parts/eval bd yet - this just based upon my read of data:

a) Tie /W to your #WR

b) Tie /G to your #RD

c) Tie D0-D7 to your #Data

d) Tie A16 (lowest) to your #Adr

e) Tie A22 (may need inverter) to #CS1

f) Tie A23 (as above) to #CS2

I am assuming/hoping that you can control the levels on A22, A23 by properly choosing an address. The /E (NE1) in your 100 pin device does not allow you to differentiate between your 2 devices - thus I have used A22 & A23. If my idea re: A22,A23 works you will have to ''insure'' that other uses of the FSMC do not inadvertently access your 2 devices. If you use the FSMC for other purposes I'm quite certain you will need stricter, qualifying logic which will require ''glue.'' Let us know - please...

e_zhui · ‎2011-05-17

Posted on May 17, 2011 at 12:46

Yes, the ''glue'' is necessary, we might have to add two OR gates,

A22 OR NE1 --> cs_dev0

A23 OR NE1 --> cd_dev1

can it work?

jj · ‎2011-05-17

Posted on May 17, 2011 at 12:46

don't think that you want ''or'' gates. (or will pass either, or both NE1 and A22, A23)

Instead you want a more restrictive, qualifying gate such as and/nand which requires that both NE1 and A22, A23 be at the qualifying level.

Recall my caution that ''if'' you use FSMC for anything else - this simple gating scheme will likely be triggered - producing ''illegal'' writes/reads of your 2 external devices. The cure here is to employ additional Adr lines - ones which are ''unlikely'' to randomly occur - and to decode them.

This may involve a quad and or even a formal decoder (138, 139).

e_zhui · ‎2011-05-17

Posted on May 17, 2011 at 12:46

yes, there are only two devices on the FSMC bus..., and A22/A23 never will be both ''0'' to prevent illegal access.