The MCU qspi peripheral is connected to serial NOR flash. Along with these connection the same qspi individual data pins are connected to 3 individual Altera FPGA for booting purpose.
qspi clock is common for all 3 FPGA.
The following operation which are working fine:
- Read and write to flash using 4 data pins is working fine.
The following problems what we are facing:
- I need to make one GPIO pin to be high Just after 8 bytes i have read from the flash.
- I kept FIFO depth 8.
and I am having doubt that where I need to alter in qspi driver such that
