Problem with SystemInit();

[chmielewski]

Posted on November 22, 2013 at 09:46

I

initialize

systeminit() in the main() and every time my Programm stops in the Code at this position in the degug-mode /* Wait till the main PLL is ready */     while((RCC->CR & RCC_CR_PLLRDY) == 0)     {     } in the ''system_stm32f4xx.c'' from coocox. what is wrong? sometimes when i diconnect my STM3240G-EVALboard and wait a few minutes, it works. but by the next code download i have the same problem. #hse-hsi-pll-rcc

[frankmeyer9]

Posted on November 22, 2013 at 10:09

what is wrong?

I would use a debugger to step into the code, and look at the PLLRDY flag. But I suspect your actual populated XTAL is not what you  are trying to set, resulting in a core frequency out of spec. Or perhaps, you don't have any external quartz at all, and need to modify SystemInit() to use HSI, the internal RC oscillator.

[jpeacock2399]

Posted on November 22, 2013 at 15:53

In general the PLL won't go to RDY because there's something wrong in the clock tree.  Either the PLL souce isn't running (check the HSERDY flag if you use the HSE as clock source) or the PLL configuration exceeds specifications.  Dump your RCC registers and make sure the settings are correct for the HSE crystal.  If you have a 25MHz crystal on the HSE then the settings that assume a 16MHz crystal aren't going to work. 

Worst case set the PLL source to the HSI and configure for 16MHz to see if the board starts.   Jack Peacock

[chmielewski]

Posted on November 25, 2013 at 08:44

Thank you for your answers.

The source for the PLL clock stands in the system_stm32f4xx.c and I had there nothing change. It´s the orginal Version source from ST. The strange is that when I disconnect the power supply from the board for a minute and turn it on, it works for awhile. /************************* PLL Parameters *************************************/ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ #define PLL_M      25 #define PLL_N      336 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P      2 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */ #define PLL_Q      7 /******************************************************************************/ void SystemInit(void)   {     /* Reset the RCC clock configuration to the default reset state ------------*/     /* Set HSION bit */     RCC->CR |= (uint32_t)0x00000001;     /* Reset CFGR register */     RCC->CFGR = 0x00000000;     /* Reset HSEON, CSSON and PLLON bits */     RCC->CR &= (uint32_t)0xFEF6FFFF;     /* Reset PLLCFGR register */     RCC->PLLCFGR = 0x24003010;     /* Reset HSEBYP bit */     RCC->CR &= (uint32_t)0xFFFBFFFF;     /* Disable all interrupts */     RCC->CIR = 0x00000000;   #ifdef DATA_IN_ExtSRAM     SystemInit_ExtMemCtl();   #endif /* DATA_IN_ExtSRAM */     /* Configure the System clock source, PLL Multiplier and Divider factors,        AHB/APBx prescalers and Flash settings ----------------------------------*/     SetSysClock();     /* Configure the Vector Table location add offset address ------------------*/   #ifdef VECT_TAB_SRAM     SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */   #else     SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */   #endif   } /******************************************************************************/ /*            PLL (clocked by HSE) used as System clock source                */ /******************************************************************************/   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;     /* Enable HSE */   RCC->CR |= ((uint32_t)RCC_CR_HSEON);     /* Wait till HSE is ready and if Time out is reached exit */   do   {     HSEStatus = RCC->CR & RCC_CR_HSERDY;     StartUpCounter++;   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));   if ((RCC->CR & RCC_CR_HSERDY) != RESET)   {     HSEStatus = (uint32_t)0x01;   }   else   {     HSEStatus = (uint32_t)0x00;   }   if (HSEStatus == (uint32_t)0x01)   {     /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */     RCC->APB1ENR |= RCC_APB1ENR_PWREN;     PWR->CR |= PWR_CR_VOS;     /* HCLK = SYSCLK / 1*/     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;            /* PCLK2 = HCLK / 2*/     RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;          /* PCLK1 = HCLK / 4*/     RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;     /* Configure the main PLL */     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);     /* Enable the main PLL */     RCC->CR |= RCC_CR_PLLON;     /* Wait till the main PLL is ready */     while((RCC->CR & RCC_CR_PLLRDY) == 0)     {     }         /* Configure Flash prefetch, Instruction cache, Data cache and wait state */     FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;     /* Select the main PLL as system clock source */     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));     RCC->CFGR |= RCC_CFGR_SW_PLL;     /* Wait till the main PLL is used as system clock source */     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);     {     }   }   else   { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */   }

[frankmeyer9]

Posted on November 25, 2013 at 09:00

The source for the PLL clock stands in the system_stm32f4xx.c and I had there nothing change. It´s the orginal Version source from ST.

No, it does not: /** * @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application

Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/ 
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

This defines a default value, which may match your setting - or not. (Provided example is from stm32f3xx.h). If everthing is otherwise correct, you can try modifying the SystemInit function for HSI, and possibly for a core clock below the specified maximum. If that gives reliable operation, you might indeed have a problem with the quartz. Measuring at the quartz pins will surely tell you nothing, because the load of the probe impedance tends to stop it oscillating.

[Tesla DeLorean]

Posted on November 25, 2013 at 16:01

Pretty sure the STM3240G-EVAL has a 25 MHz clock.

+1 on the HSI 16 MHz test, both directly, and via PLL If the PLL is not stable at 168 MHz in any configuration, would look to supplies and VCAP pins. Where is CooCox calling SystemInit(), CMSIS wants it called prior to main()

[chmielewski]

Posted on November 27, 2013 at 13:49

In Coocox you must calling SystemInit() by your self and I call it in the main();

here my source in the stm32f4xx.h #if !defined  (HSE_VALUE)   #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /**  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup    Timeout value    */ #if !defined  (HSE_STARTUP_TIMEOUT)   #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0500)   /*!< Time out for HSE start up */ #endif /* HSE_STARTUP_TIMEOUT */    #if !defined  (HSI_VALUE)      #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */  after I write in the Defined Symbols of Coocox this HSE_VALUE = 25000000 it works without problems. maybe this was the problem.