2014-12-23 11:06 AM
Not sure if this is the correct term but to aid in laying our a pcb for my project where I have three 16 pin devices that need to connect to i/o ports. I would like to know how much of a performance hit will the processor take when I connect each 16 pin device cleanly from a layout point of view but mixing up the ports. For example:
porta1 - deviceApin1 porta2 - deviceApin2 porta3 - deviceApin3 porta4 - deviceApin4 portb1 - deviceApin5 portb2 - deviceApin6 portb3 - deviceApin7 portb4 - deviceApin8 portc1 - deviceApin9 portc2 - deviceApin10 portc3 - deviceApin11 portc4 - deviceApin12 I was under the impression that you can define a Virtual port made up of any of the pins from the ''real'' ports and act on the virtual port the way you would a real port. For example if you wanted to make a variable equal to the VirtualPortx it would be the same command as making a variable equil to PortA. Or if you wanted to make the outputs of a virtual port = ''1001001111001001'' a single command would do it... Thanks, I'm the pcb guy not the software guy... Kevin2014-12-23 11:29 AM
I was under the impression that you can define a Virtual port made up of any of the pins from...
From where? Academic materials or chip documentation? This isn't VHDL/Verilog, or an FPGA design. Swizzling bit positions, and writing to different port bank registers, is an inefficient, multi-step process. Try to get data and address buses using linear runs of pins, control signals can use different pins/banks. Pins you want driven by hardware resources, if FSMC (external memory bus), TIMers, etc. can have very specific pin usage requirements. Refer to the Data Sheet/Manual. Talk to the software guy, or the design engineer on the project.2014-12-23 11:32 AM
Thanks very much Clive.
Regards, Kevin2014-12-23 11:39 AM
Begs the question, why on earth are the pins for the different ports spread all over the chip (STM32F407 100 pin )...
Kevin