PLL Settings

[qwer.asdf]

Posted on October 23, 2015 at 14:43

Hi, is there any difference how exactly I'm getting the desired clock speed on SYSCLK through PLL? For example, let's say I want to have 48MHz on SYSCLK on STM32F407, using a 8 MHz HSE and the PLL. One way of doing it would be this:

HSE = 8MHzM = 8 N = 384 P = 8 Q = 8 -------- SYSCLK = 48MHz Another way of doing it would this: HSE = 8MHz M = 4 N = 96 P = 4 Q = 4 -------- SYSCLK = 48MHz So my question is: is one of these two ways better than the other (i.e. lower jitter, or lower power consumption), and why? Thank you.

[waclawek.jan]

Posted on October 23, 2015 at 22:54

Obviously no, and the PLLs in various sub-families differ significantly from each other - for example, while in 'F4 the PLL input clock range is 1-2MHz, in 'F1 this range is 1-25MHz.

JW

[mikael239955_stm1_st]

Posted on October 25, 2015 at 01:26

There are numeror bugs in CUBE that's why i only use it for pin mapping and even that dont work 100% depending device you are selecting and it has from the start and it is with the

latest release.