At the end of NVIC_SCBDeInit I see these instructions:
[...]
SCB->CFSR = 0xFFFFFFFF;
SCB->HFSR = 0xFFFFFFFF;
SCB->DFSR = 0xFFFFFFFF;
The first one is a status register. Why writing it?
For the second one the manual states:
"This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0"
... "DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable."
The third one, DFSR does not exist in Cortex manual....
I am using STM32F103 and Cortex™-M3 Devices - Generic user manual
