> 1) The reset 'architecture', and how it links into / controls other parts of the processor (especially ports & outputs).
From RM0033:
> A system reset sets all registers to their reset values except the reset flags in the clock
> controller CSR register and the registers in the Backup domain (see Figure 4).
> A system reset is generated when one of the following events occurs:
> 1. A low level on the NRST pin (external reset)
[...]
Throughout the RM, the reset state of all registers is given in the description of those registers, including GPIO.
I don't quite understand what exactly do you mean by the remaining questions. There may be synchronous paths in the reset mechanism and the mechanisms between the internal registers and pins, but upon reset the system clock in RCC is also switched to HSI which is switched on upon reset - see reset value of RCC_CR and RCC_CFGR. Worst case HSI startup time is given in DS.
You may want to ask whether the GPIO reset is asynchronous, but that's a question you are not likely to be answered here. Note, that this is a primarily user-driven forum, so more in-depth question should be asked ST directly.
JW
