Just got a weird problem with a NOR flash, memory mapped on FMC, address 0x60000000.
The model is IS29GL128, 16 MB.
Most of the code borrowed from eval. board examples.
Basically it works (write, read, erase). But during mass erase the systick interrupt does not arrive until the erase ends. It takes almost 120 seconds.
During one-sector erase or buffer write the tick interrupt arrives properly, I can measure the time and it looks correct.
I tried to break into debugger during the mass erase - it lags, then shows something weird, won't post it now.
After the mass erase ends, the usual code for NOR polling status returns success and systick interrupt arrives again.
Any explanation of this behavior?
The code runs in AXI RAM, data and stack in DTCM; none of my code or data is on this flash. Accessing it only via pointers.
Below is setup code:
void MX_FMC_NOR_Init(void)
{
FMC_NORSRAM_TimingTypeDef Timing = {0};
hnor1.Instance = FMC_NORSRAM_DEVICE;
hnor1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* hnor1.Init */
hnor1.Init.NSBank = FMC_NORSRAM_BANK1;
hnor1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hnor1.Init.MemoryType = FMC_MEMORY_TYPE_NOR;
hnor1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
hnor1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hnor1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hnor1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hnor1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hnor1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hnor1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hnor1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_ENABLE;
hnor1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hnor1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
hnor1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
hnor1.Init.PageSize = FMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 255;
Timing.BusTurnAroundDuration = 15;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FMC_ACCESS_MODE_A;
if (HAL_NOR_Init(&hnor1, &Timing, NULL) != HAL_OK)
{
Error_Handler( );
}
}
#define MPU_set_(p, tex, c,b,s) \
(p)->TypeExtField = (uint8_t)(tex); \
(p)->IsCacheable = (uint8_t)(c); \
(p)->IsBufferable = (uint8_t)(b); \
(p)->IsShareable = (uint8_t)(s);
#define MPU_set_StronglyOrdered(p) MPU_set_((p), 0, 0,0,0)
static void init_MPU_for_FMC()
{
HAL_MPU_Disable();
MPU_Region_InitTypeDef mis = {0};
mis.SubRegionDisable = 0x0;
mis.AccessPermission = MPU_REGION_FULL_ACCESS;
mis.Enable = MPU_REGION_ENABLE;
// SDRAM:
mis.Number = 1;
mis.BaseAddress = SDRAM_BANK_ADDR; //0xC0000000;
mis.Size = MPU_REGION_SIZE_64MB;
MPU_set_StronglyOrdered(&mis);
mis.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
HAL_MPU_ConfigRegion(&mis);
// NOR:
mis.Number = 2;
mis.BaseAddress = NOR_BANK_ADDR; //0x60000000;
mis.Size = MPU_REGION_SIZE_16MB;
HAL_MPU_ConfigRegion(&mis);
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
