Posted on August 24, 2013 at 19:12Hi all,
I'm designing a MICROSD SDIO bus on a future PCB with a splitted ground plane below all D0-D3, CMD, CLK and SD_VDD to decrease noise, but I can't find a way to ''totaly'' cover the D0 and D1 traces (LQFP64 STM32F103) : this 2 traces will be partially ''uncovered'', but they won't cross between 2 adjacent splitted ground planes.
My question is : how do you know what VDD and VSS pin will be prefered by current return path, depending on the pin location on the chip ?
And does all the VSS and VDD are connected internaly to the chip ?
Tx
