Need help for STM32F103RD PLL setup

[giaan086]

Posted on March 06, 2016 at 06:32

Hi everyone! i got some prob when i trying to setup PLL run at full speed 72MHz. Here is my code

RCC_CR_bit.HSEON = 1; 
//enable HSE

while
(!RCC_CR_bit.HSERDY); 
//wait for HSE ready

//------------------------------PLL------------------------------------------

RCC_CFGR_bit.PLLSRC = 1; 
//PLL source = HSE (0:HSI/2, 1:HSE)

RCC_CFGR_bit.PLLXTPRE = 1; 
//PLL = HSE/2 = 8MHz (0:not div, 1:div by 2)

RCC_CFGR_bit.PLLMUL = 0x07; 
//PLL = HSE x 9 = 72MHz (<=72MHz)

RCC_CFGR_bit.USBPRE = 0; 
//USB = PLL/1.5 = 48 MHz (0:div by 1.5, 1:not div)

RCC_CFGR_bit.PPRE1 = 0x05; 
//HCLK prescaler (<=36MHz)

RCC_CR_bit.PLLON = 1; 
//enable PLL

while
(!RCC_CR_bit.PLLRDY); 
//wait for PLL ready

//---------------------------------------------------------------------------


RCC_CFGR_bit.SW = 0x02; 
//select system clock (HSI = 00, HSE = 01, PLL = 10)

while
(!(RCC_CFGR_bit.SWS==0x02)); 
//wait for system clock turn into PLL (HSI = 00, HSE = 01, PLL = 10)

RCC_CR_bit.HSION=0; 
//turn off HSI to save power


//--------------------------Peripheral---------------------------------------

RCC_AHBENR = 0; 
//bit => 10:SDIO, 8:FSMC, 6:CRC, 4:FLITF, 2:SRAM, 1:DMA2, 0:DMA1

RCC_APB2ENR = 0; 
//bit => 21:TIM11, 20:TIM10, 19:TIM9, 15:ADC3, 14:USART1, 13:TIM8, 12:SPI1, 11:TIM1, 10:ADC2, 9:ADC1, 8:IOPG, 7:IOPF, 6:IOPE, 5:IOPD, 4:IOPC, 3:IOPB, 2:IOPA, 0:AFIO

RCC_APB1ENR = 0; 
//bit =>29:DAC, 28:PWR, 27:BKP, 25:CAN, 23:USB, 22:I2C2, 21:I2C1, 20:UART5,19:UART4, 18:USART3, 17:USART2, 15:SPI3, 14:SPI2, 11:WWDG,8:TIM14, 7:TIM13, 6:TIM12, 5:4:TIM6, 3:TIM5, 2:TIM4, 1:TIM3, 0:TIM2

Im using xtal 16MHz and debugger show that my program stuck at switching system clock source to PLL. when I lower the PLLMUL my chip work again. I think I misunderstood something when reading manual. Another question: I read some other code in which they using &=, |=,... to set or reset a bit in a register. Does it better than using <register_name>.<bit_name> = 0 (or =1)? Thanks for reading :'') #stm32f1

[Tesla DeLorean]

Posted on March 06, 2016 at 14:26

Do you set up the flash wait states and APB clocks first?

Doing multiple load-stores on the same register seems like the least efficient method possible.

[clark2]

Posted on March 07, 2016 at 06:50

I believe you want something like this:

RCC->CFGR = RCC_CFGR_PLLSRC_HSE
| RCC_CFGR_PLLXTPRE_HSE_Div2
| RCC_CFGR_PLLMULL9
| RCC_CFGR_HPRE1_DIV2;
RCC->CR |= RCC_CR_PLLON;
while
(!(RCC->CR & RCC_CR_PLLRDY)); 
FLASH->ACR |= FLASH_ACR_LATENCY_2;
RCC->CFGR |= RCC_CFGR_SW_PLL;

You may also want to add configuration for PCLK1, PCLK2, and ADCCLK... or not.

[giaan086]

Posted on March 10, 2016 at 06:13

I setup the FLASH waitstate and it work like a charm =))

thanks so much.

[clark2]

Posted on March 10, 2016 at 21:53

Be aware that, in line 8 of your code listed above, the code is configuring PPRE1 (PCLK1) while the comment mentions HCLK.

[giaan086]

Posted on March 11, 2016 at 05:34

thanks. I read the manual again. It must be APB1 clock.