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LPTIM match interrupt discrepancy on STM32U5



We are working with STM32U585AI processor. Our software is based on an RTOS and we are using LPTIM to generate OS ticks.

Our system runs from either PLL@160MHz or HSI@16MHz depending upon system load. LPTIM is fed directly from LSE@32768Hz.

We are familiar with LPTIM's "quirks", as described in the github link below and have implemented them in our project:

There is one particular "quirk" of LPTIM, that seem to be dependent on SysClock frequency (in our case, sysclock = HCLK = PCLK1 = PCLK2 = PCLK3).

If the system is running from PLL@160MHz, then the match condition is "CNT >= CCRn && CNT != ARR". We detect this condition and set a flag to identify that the next match interrupt would be a false match interrupt. This way we can filter match interrupts that happen when CNT and CCRn actually match from cases where the match interrupt occurs just because CNT became larger than CCRn due to timer update.

The criteria mentioned above is failing when system is running from HSI@16MHz. It fails because LPTIM does not generate a false match interrupt if CNT becomes larger than CCRn. This leads our software to miss actual match interrupts because it thinks that the match interrupt is a false match interrupt.

I could not find any reference to this behavior in neither reference manual nor the errata sheet. Could someone please clarify the cause of this strange behavior (frequency dependent match interrupt) from LPTIM?



ST Employee

Hi IrfanShahid

Your question has been routed to the online support team. A case has been created and you'll be contacted shortly.

Kind Regards


STMicro Support