Issue with USART RXFIFO threshold configuration

CTabo.1 · ‎2024-02-08

Hello,
I am developing an application on STM32H563 MCU and NUCLEO board.

I have the following problem when trying to configure USART2 RXFIFO threshold.

In particular, on a transmission completed event, inside the ISR, I need to configure the RXFIFO threshold based on the expected number of bytes to receive.
I try to do this, using the LL_USART_SetRXFIFOThreshold(), but I see that it doesn't have effect on the RXFTCFG bits of register CR3, that remains stuck at 0.

What am I doing worng?

Regards,
Carlo

tjaekel · ‎2024-02-09

Often, you can change the peripheral (device) config only when it is disabled. Disable the USART and change it, enable afterwards again. I do not think it is good idea this stuff inside an ISR.

BTW: FIFO is not related to "expected number of bytes to receive". For instance, if you expect 100 bytes - you cannot configure FIFO for 100 bytes (the FIFO is not so large).

The FIFO is not related to number of transferred bytes: it is there to help FW to relax (to have option when FW is busy N bytes are not lost). Check the FIFO size possible.
BTW: a FIFO can make things also a bit more complicated (e.g. received byte still sitting in FIFO: you have to check on reception if there is still something in FIFO).

Do not use a FIFO as a "receiver buffer": it is there just to make the FW a bit more relaxed, when to read the FIFO.
If you use FIFO as receiver buffer - check the FIFO size (and make sure that transmitter has stopped sending data, otherwise FIFO overflows).

View solution in original post

tjaekel · ‎2024-02-09

Often, you can change the peripheral (device) config only when it is disabled. Disable the USART and change it, enable afterwards again. I do not think it is good idea this stuff inside an ISR.

BTW: FIFO is not related to "expected number of bytes to receive". For instance, if you expect 100 bytes - you cannot configure FIFO for 100 bytes (the FIFO is not so large).

The FIFO is not related to number of transferred bytes: it is there to help FW to relax (to have option when FW is busy N bytes are not lost). Check the FIFO size possible.
BTW: a FIFO can make things also a bit more complicated (e.g. received byte still sitting in FIFO: you have to check on reception if there is still something in FIFO).

Do not use a FIFO as a "receiver buffer": it is there just to make the FW a bit more relaxed, when to read the FIFO.
If you use FIFO as receiver buffer - check the FIFO size (and make sure that transmitter has stopped sending data, otherwise FIFO overflows).

CTabo.1 · ‎2024-02-13

Thank you @tjaekel,

I was used to consider FIFO as "receive buffer", because of my experience with TI DSP, where USART FIFO handling is more flexible.

In that case, indeed, I could modify the deeper FIFO length (16 characters) on the fly, without enabling/disabling USART, setting it to the precise number of characters expected.

Regards,
Carlo