2022-03-26 07:03 AM
Hi!
ST manual PM0253:
[31:9] TBLOFF Vector table base offset field. It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
[8:0] - Reserved
Arm v7-M Architecture Reference Manual:
Bits[31:7] of the vector table address.
Older documentation describes this field as the vector table address offset. The description
in this manual clarifies the use of this register.
Bits[6:0] - Reserved
Is there wrong assignment description in PM0253?
Solved! Go to Solution.
2022-03-26 07:24 PM
For STM32H7 the vectors address must be aligned at least on 0x400
Learned in a hard way ((
See at end of this thread. @Piranha explains it.
Yes, on M7 VTOR is the vector table base address - including the lower zero bits - because of alignment requirement.
2022-03-26 07:24 PM
For STM32H7 the vectors address must be aligned at least on 0x400
Learned in a hard way ((
See at end of this thread. @Piranha explains it.
Yes, on M7 VTOR is the vector table base address - including the lower zero bits - because of alignment requirement.
2022-03-26 07:32 PM
It depends on how the ARM IP builds based on the number of interrupt used by the NVIC, unused inputs are optimized away.
2022-03-28 08:21 PM
Great thanks for additional material.