is it possible not to reset the SRAM (D2 Domain) when M4 is enabled?

[RolfStDK]

Hi all,

    Working on STM32H745: when enabling the M4 at M7 main(), the 'D2 domain' SRAMs (1,2,3) are being reset, causing issue, as the M7 and the OS are using these SRAMs, prior of the M4 enable (RCC register). 

Is there any option not to reset the SRAM at the M4 enable?

Tried to remove the D2 SRAM from the M7 linker file, but then had insufficient memory...

Thanks in advance 🙂

Rolf

[STOne-32]

Dear @RolfStDK ,

Your  case has been escalated to our Online support and my colleagues will be back to you . In meantime, can you try first to enable AHB clocks of SRAM memorizes (1,2and 3)  in D2 domain , by setting the corresponding bits in the RCC_AHB2ENR . You can add that in system_stm32h7xx.c before vector table location.  Hope it helps you .

Cheers,

STOne-32

[Roger SHIVELY]

Hello @RolfStDK ,

There has been a case created to resolve this question and we will be reaching out to you directly.

Regards,
Roger