IRQ Questions

geoff2399 · ‎2010-07-09

Posted on July 09, 2010 at 13:45

IRQ Questions

epassoni950 · ‎2011-05-17

Posted on May 17, 2011 at 13:58

Hello,

1) Yes, an IRQ of higher priority can interrupt an already running IRQ handler. For example if priority of SYSTICK is 7 and priority of USART1 is 6, receiving a character on USART1 can interrupt SYSTICK interrupt routine. Another example if USART1 and USART2 have the same priority, and a character is received on USART2 while USART1 interrupt is running, USART2 interrupt start only when USART1 interrupt terminate.

2) I used a little FreeRTOS with Cortex-M3 and what I seen is that FreeRTOS use PENDSV interrupt. A task switching don't occur in interrupt handler but interrupt handler arm a PENDSV interrupt when interrupt handler need a task switching. When all interrupt handler have terminated, Cortex-M3 execute PENDSV interrupt. Real task switching occurs in PENDSV interrupt handler. It is possible to have many interrupts which need task switching before PENDSV is executed. In that case, it is the task with the highest priority which is activated during PENDSV interrupt.

Regards

Eric

chikos332 · ‎2011-05-17

Posted on May 17, 2011 at 13:58

Hi,

I'll try to answer only the easy questions :)

1- Yes an IRQ can interrupt another ISR if the NVIC peripheral is configured correctly (You won't find such information neither in STM32 Reference manual nor in google, the only document you can refer to is the ARM technical manual: DDI0337E_cortex_m3_r1p1_trm).

I have to tell you from now: ARM doc about NVIC really ''sucks'' it just tell what are the name of bits and registers and a very very short description about functionalities.

I really wonder why ST doesn't provide some useful documentation for this particular IP???

But fortunately, there are some instructive examples about the NVIC:

in ST library

http://www.st.com/stonline/products/support/micro/files/stm32f10x_stdperiph_lib.zip

look into folder ''Project\STM32F10x_StdPeriph_Examples\NVIC\''.

2- I don't think that it is advised to perform task switching into ISR, but I think it is possible if the task switching is the last operation in the ISR (thus you will not return to the ISR again). This point really depends on the RTOS you use, so refer to FreeRTOS forum/doc for such questions (There is already a project of FreeRTOS on STM32 with all needed configurations and some useful examples of how to use interrupts).

For the other points I can't help you.

Cheers.

t1 · ‎2011-05-17

Posted on May 17, 2011 at 13:58

The interrupt system for Cortex-M3 is completely different to that of the ARM7, ARM9 etc. so ignore everything you read about for interrupts on those chips.

For Cortex-M3, the interrupt system is similar to used on the Motorola 68000 and ColdFire microprocessors (with some additional refinements). So documentation on these might be helpful.

I don't have any answers for questions 2 and 3.

var2 · ‎2011-05-17

Posted on May 17, 2011 at 13:58

There is document PM0056 (lost between the flash programming manuals), where you can find a detailed description of NVIC and other Cortex-M3 general features.

http://www.st.com/stonline/products/literature/pm/15491.pdf

phil239955_stm1 · ‎2011-05-17

Posted on May 17, 2011 at 13:58

There is also a good Hitex guide....

http://www.st.com/mcu/download2.php?file=1221142709.pdf&info=STM32F103C8 Reference Manual &url=/mcdfiles/1221142709.pdf

Worth spending some time reading up as there are many features which are good to know about and use!