Skip to main content
HBida
HBida
Associate III
November 24, 2019
Question

Interfacing STM32F412 and using DFSDM with 32Msample/S 1-bit Delta Sigma ADC

  • November 24, 2019
  • 3 replies
  • 1529 views

Hello,

We need to use analog front-end providing a 1-bit Delta-Sigma interface (clock output + I channel and Q channel) with STM32F411 or STM32F412, initially we planned to use the STM32F411 but i noticed that the STM32F412 has a DFSDM peripheral which would help a lot with such interface. Unfortunately the datasheet states that the maximum speed of the DFSDM interface is 20MHz, our front-end can only provide 32MSample/S or 36MSample/S clock (tied to the onboard TCXO). IS there a way to solve this problem? On the STM32F4 serie apparently the SPI and I2S interfaces can reach 50Mbit/S ("Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol") so, is there a way to use the SPI interface in our case and also benefit from the DFSDM periphearl?

Thanks.

This topic has been closed for replies.

3 replies

waclawek.jan
waclawek.jan
Super User
November 24, 2019

I don't think you can use DFSDM under these conditions. Both the DS and RM are very specific in that 20MHz is the maximum possible clock frequency.

There's a parallel input to the DFSDM which can go up to 20MHz too, but that needs signed 16-bit values, ie. you'd already need PCM rather than PDM values, so you'd need to pre-filter somehow in software - and I don't believe it's possible at that data rate - except if you would not need the data continuously but in batches, and batches would be short enough to fit into some of the internal memory, and then the data could be processed off-line, then maybe...

JW

HBida
HBidaAuthor
Associate III
November 24, 2019

thank you for the input, yes that is my fear, i will ask an official statemnt to ST about this, in fact other than the interface issue my fear is that the DFSM cannot handle processing the datas at this rate.

What about using shift registers? there are many in the TI 74 familly that can handle 70MHz and more, we couldnt use that to get the datas of both lane at once (8+8bit) to a parallel interface?

waclawek.jan
waclawek.jan
Super User
November 25, 2019

> my fear is that the DFSM cannot handle processing the datas at this rate.

That's what the 20MHz limit is all about, it's not a limit on the inputs as such.

> shift registers

That's what SPI is as you've mentioned. Again, problem is not in shifting data in, but what would you do with them, then.

> both lane

What lane?

JW

Terms & ConditionsAccessibility statement