Posted on June 03, 2013 at 17:42Seek Cortex-M0 core documentation from ARM
Things like loads and stores will be impacted by assorted bus speeds, wait states and bus contention.
For practical purposes you should benchmark your code in a working system using the settings you plan on using. Utilize a scope, and evaluate transitions on GPIO pins. The M0 does not have a core cycle counter available in the ITM like M3/M4 cores do.
