Posted on May 17, 2011 at 13:14Hi All!
I have another I2C problem (I allready searched the forum but didn't found anything related):
I am using my own ISR code (not depening on the fwlib) only triggered by event-irqs. Thus the isr gets called when the BFT bit gets set.
In master transmitter mode I set the STOP bit in CR1 after the last byte has been transmitted. I can see the stop condition happen on the bus.
The problem is that even after the stop condition the STOP bit does not allways gets cleared in CR1. Thus when issuing the next START I get a start condition immediately followed by a stop condition.
As a woraround I am currently clearing the STOP bit when setting the START bit. But I still have a bad feeling doing it that way.
Has anyone observed that and has a solution, idea?
BTW: What exactly does the TRISE register do?
Thanks,
Clemens
