I2C Clock Control - Fast Mode

[george239955_st]

Posted on April 17, 2013 at 12:12

Section 2.6.8 of RM0038 states:

''fPCLK1 must be a multiple of 10MHz to reach the 400kHz maximum I2C fast clock mode''how can I calculate the maximum I2C frequency I can achieve using a 4.2MHz fPCLK1this information doesn't seem to be in the reference manual.

[Tesla DeLorean]

Posted on April 17, 2013 at 13:57

@4.2 MHz, I2C 350 KHz

Per I2C_CCR 2:2 Ratio Duty Divisor 4 16:9 Ratio Duty Divisor 25, not workable here CCR = 3, F/S=1, DUTY = 0 (4200000 /4) / 3 = 350000

[george239955_st]

Posted on May 15, 2013 at 15:53

''fPCLK1 must be a multiple of 10MHz to reach the 400kHz maximum I2C fast clock mode''

does this mean that fPCLK must be an integer multiple of 10MHz or is it OK for it to be 10MHz or greater?

[Tesla DeLorean]

Posted on May 15, 2013 at 16:07

does this mean that fPCLK must be an integer multiple of 10MHz or is it OK for it to be 10MHz or greater?

It must be divisible by 25 (ie 10 MHz / 25 = 400 KHz), so 20 MHz would be workable with further divide by 2, but 11 MHz would result in a rate higher than 400 KHz, or significantly lower (220 KHz for the 16:9 duty mode).

[george239955_st]

Posted on May 15, 2013 at 16:36

looking at the clock tree on page 90 of RM0038 it does not look like we can achieve 400kbps I2C using either the Multi Speed Internal or High Speed Internal and we would have to use an External Clock?

[Tesla DeLorean]

Posted on May 15, 2013 at 18:18

Indeed, the joys of limited integer dividers designed with counters.