I'm currently integrating a Micron MT29F1G01ABAFDWB NAND flash with a STM32L4R5ZIT using its OctoSPI peripheral. According to Table 119 on page 556 of the SMT32l4+ reference manual RM0432, Micron mode is not supported. Which OSPI modes does this include?

[AHart.3]

I'm currently trying to integrate a Micron MT29F1G01ABAFDWB NAND flash with a STM32L4R5ZIT using its OctoSPI peripheral. A colleague of mine found Table 119 on page 556 of the SMT32l4+ reference manual RM0432 that seems to indicate that our MCU does not support Micron mode. I have attached a screenshot of the relevant table for ease of reference. The interesting thing is that CubeMX does allow one to select Micron mode even though the STM32L4R5ZIT MCU was chosen for the CubeMX project.

From page 556 in the reference manual, the register settings indicate that using regular command protocol does not affect the functionality. Does the Micron mode then only refer to polling more and memory mapped mode? Also, if MTYP[2:0] = 010 is used, "Standard Mode" is selected. What does this mode entail? It isn't listed in CubeMX or the STM32 drivers.

I would like to make sure that there is in fact an incompatibility and if so if there is a work around. To what extend does the Micron or Macronix mode affect the behaviour of the OctoSPI peripheral?

[Tesla DeLorean]

I don't see any attachment

The L4R5 should have timing diagrams in the reference manual. It would be interesting to know if any of the ST staff or FAE have evaluated this part as part of the QSPI/OSPI validation efforts.

Datasheet for one of the close variants

https://datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf

[Andreas Bolsch · Accepted solution]

Micron vs. Macronix mode affects only byte ordering in octal-DTR mode,

description of OCTOSPI_DCR1:

Bits 26:24 MTYP[2:0]: Memory type

This bit indicates the type of memory to be supported.

000: Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular SPI protocol in Octal,

Quad, Dual and Single modes

Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal.

This is the default value and care must be taken to change MTYP[2:0] for memories different

from Micron.

001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in

Octal/Quad/Dual/Single modes

010: Standard mode

011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular SPI protocol in

Octal/Quad/Dual/Single modes with dedicated address mapping.

100: HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit

DTR mode must be selected.

101: HyperBus register mode, addressing register space. The memory-mapped accesses in

this mode must be non-cacheable, or Indirect read/write modes must be used.

Others: Reserved

As long as you don't use octal DTR, this doesn't matter at all. If you do, you would have to compensate the byte-swapping, and maybe invert DQS signal as well.

[Tesla DeLorean]

My sense was that it would be workable. Doubt the burst bandwidth is going to materially impact overall performance, other things will bottleneck faster.