How would interrupt flag be cleared by "writing the LPTIM_ICR bit in the LPTIM_ISR register"?

[waclawek.jan]

The LPTIM erratum "MCU may remain stuck in LPTIM interrupt when clearing event flag" (to be found in errata of STM32 having LPTIM, which got updated since cca the end of 2018 -- ST please update *all* errata timely!) contains this description:

This limitation occurs when the LPTIM is configured in interrupt mode (at least one interrupt is enabled) and the software clears any flag by writing the LPTIM_ICR bit in the LPTIM_ISR register.

There is no LPTIM_ICR bit. LPTIM_ICR is the register in by writing individual bits, interrupts flags in the LPTIM_ISR register can be cleared.

ST, please correct this. Please provide a complete description, upon which the user can decide how exactly to implement the workaround, not relying on any "library" implementation.

This is not the only case of messy description in errata. Errata are an important part of the documentation. ST, please review all errata for comprehensibility of the description.

JW

[Amel NASRI]

Hi Jan,

I agree with you that current description is not enough clear. The sentence creating confusion will be reformulated as following: "This limitation occurs when the LPTIM is configured in interrupt mode (at least one interrupt is enabled) and the software clears any flag in ISR register by writing the corresponding bit in LPTIM_ICR register."

Thanks for bringing such ambiguity to our attention, this is the more helpful way to improve documentation content.

-Amel

[waclawek.jan]

Thanks, Amel.

Jan

@Amel NASRI​ 

[Amel NASRI · Accepted solution]

Hi @Community member​ ,

Coming back to this old discussion to keep you informed that update is already done in ES0393.

For sure, update will be done also on other erratasheets when new releases will be scheduled for them.

-Amel