How to use Interrupt enable Registers?

[Muzahir Hussain]

Posted on November 11, 2017 at 18:15

In Cortex m3/m4, Interrupt Set Enable Registers is used to enable/disable the interrupts. How would we know which bit corresponds to which interrupt?

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/Cihcajhj.html

 does not give a clue on this.#interrupt-handler #stm #stm32f103 #interrupt-issue

[Tesla DeLorean]

Posted on November 11, 2017 at 21:32

The NVIC interrupts are implementation specific (ie ST, ATMEL, NXP, etc), so look at the Reference Manual for the part you are using.

Review Vector Table, there is a linear application of bits and registers within the NVIC

So EXTI0 is interrupt #6

[Muzahir Hussain]

Posted on November 11, 2017 at 22:04

 ,

 ,

So this means if I want to enable hardfault and memManage Fault, which is interrupt no. 3 and 4 according to

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABIFJFG.html

, ,I can simply do this,

♯ define NVIC_ISER (*((volatile unsigned long*) 0xE000E100))

NVIC_ISER = 0x00000018, // Interrupt set enable register

Right?

[Tesla DeLorean]

Posted on November 11, 2017 at 23:44

>>Right?

No, they are SYSTEM EXCEPTIONS, not INTERRUPTS (IRQs)

The IRQs are in the NVIC, the System Exceptions are not. In the table above IRQ ♯ 0 is WWDG, IRQ ♯ 3 is RTC_WKUP

http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihhjgdh.html

 

Use SCB->SHSCR |= (1 << 16); to enable the Memory Manager

Would suggest ORing new bits on to registers rather than assuming initial/current content