2021-12-08 12:52 PM
I can not start transfer via SWO to STM32H743.
Port PB3 initialized clock feed.
Initialized SWO:
*(__IO uint32_t*)(0x5C001004) |= 0x00700000; // DBGMCU_CR D3DBGCKEN D1DBGCKEN TRACECLKEN
//UNLOCK FUNNEL
*(__IO uint32_t*)(0x5C004FB0) = 0xC5ACCE55; // SWTF_LAR
*(__IO uint32_t*)(0x5C003FB0) = 0xC5ACCE55; // SWO_LAR
//SWO current output divisor register
//This divisor value (0x000000C7) corresponds to 400Mhz
//To change it, you can use the following rule
// value = (CPU Freq/sw speed )-1
*(__IO uint32_t*)(0x5C003010) = ((SystemCoreClock / 2000000) - 1); // SWO_CODR
//SWO selected pin protocol register
*(__IO uint32_t*)(0x5C0030F0) = 0x00000002; // SWO_SPPR
//Enable ITM input of SWO trace funnel
*(__IO uint32_t*)(0x5C004000) |= 0x00000001; // SWFT_CTRL
// Configure GPIOB pin 3 as AF
*(__IO uint32_t*)(0x58020400) = (*(__IO uint32_t*)(0x58020400) & 0xffffff3f) | 0x00000080;
// Configure GPIOB pin 3 Speed
*(__IO uint32_t*)(0x58020408) |= 0x00000080;
// Force AF0 for GPIOB pin 3
*(__IO uint32_t*)(0x58020420) &= 0xFFFF0FFF;
uint32_t SystemCoreClock = 480000000;
include printf:
int _write ( int file, char *ptr, int len )
{
int i = 0;
for ( i = 0; i < len; i++ )
ITM_SendChar ( *ptr++ );
return len;
}
Calls when passing a message through printf (); Checked set the brepoint in _write the moment the transfer is called
I checked the PB3 leg with an oscilloscope there is no signal.
The call to _write is passed to ITM_SendChar (* ptr ++); there is.
What is the matter, I ask for help.
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2021-12-08 03:00 PM
The ST-LINK/V2 on the original NUCLEO-H743ZI ran at 2 MHz
The frequency on the ZI2 version with the ST-LINK/V3 ran a lot faster.
I'd probably bring up the STM32 Cube Programmer SWV Window, and change the 2000000 to 24000000 or whatever you've selected as the connection speed. It's a ratio between the MCU clock, and the SWD clock..
The familiar looking code also assumes GPIOB clock has been enabled.
2021-12-09 02:15 AM
In my code I have an ITM initialization:
// Configure ITM
ITM->LAR = 0xC5ACCE55 ; // ITM Lock Access Register, C5ACCE55 enables more write access to Control Register 0xE00 :: 0xFFC
ITM->TCR = 0x00010001 ; // ITM Trace Control Register
ITM->TPR = ITM_TPR_PRIVMASK_Msk ; // ITM Trace Privilege Register. All stimulus ports
ITM->TER = portMask ; // ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port.
ITM/SWO works only in debug mode