2018-12-12 09:09 AM
A reference to an existing explanation would be fine.
I can't find a reference manual
2018-12-12 11:02 AM
I do know that SCL is derived from the core's bus clock and there needs to be an even divisor between the bus clock and 400KHz. So you may need to change your bus frequency or if you are using axi, you can just change the frequency of the core's axi clk.
2018-12-13 05:33 AM
Hi @briancavanagh91 ,
There is an application note dedicated for STM32F3xxxx and STM32F0xxxx that describes how to configure I2C_TIMINGR register.
This application note should help you to understand the theory: https://www.st.com/resource/en/application_note/dm00074956.pdf.
Then, if you use the STM32CubeMX tool and enable the I2C peripheral, it will calculate the suitable configuration for TIMINGR register depending on the values you select for timing parameters and on your clock settings.
-Amel
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