How to reset slave timer in gated mode?

[adawang150]

Posted on September 20, 2016 at 05:05

How to make automatic reset of slave timer in gated mode in STM32 mcu?

Summary:

I've done synchronization between 2 timers: Timer#1 is configured as a slave in gated mode, Timer#2 is configured as a master, it toggles its output compare channel, which is an input for slave timer.

The timer overview (AN4013 application note on timers) states that: ''the counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low''. And it works just like that: when output of master timer becomes high, slave timer starts, and when it becomes low - it stops, but notreset, which leads to undefined behaviour - after changing output from ''high'' to ''low'', line sometimes becomes low (as I need it to) and sometimes doesn't change (standing high).

So the question is, if it possible to reset slave timer on trigger becomes low?

PS: I'm using

http://www.kynix.com/Detail/1183926/STM32F103C8T6.html

microcontroller

[waclawek.jan]

Posted on September 20, 2016 at 23:55

> So the question is, if it possible to reset slave timer on trigger becomes low?

Not through the timer linking facility. The slave mode controller is pretty simplistic, you can't use more than one function of it at a time. But maybe you might achieve what you intend by triggering a DMA transfer by the master timer at the trailing edge of the master's pulse, which would write 0 into slaves' CNT. JW

[Arek P]

Posted on October 12, 2017 at 21:34

Problem is old and propably already solved but as there is no solution here I would like to share my way to solve it.

Yes, it is possible to reset slave timer when trigger becomes low. It cannot be done automatically (at least I do not know how).

I have used interrupt on master to reset slave counter.

Simply add interrupt on CC (timer 1 is master)

TIM1->DIER = TIM_DIER_CC1IE; // interrupt 

and clear slave (timer 2) counter in interrupt

__attribute__((interrupt)) void TIM1_CC_IRQHandler(void){

   if (TIM1->SR & TIM_SR_CC1IF){      TIM1->SR = ~TIM_SR_CC1IF;       TIM2->CNT = 0; // reset TIM2 counter    }}

In this case every time trigger becomes low and stop slave timer its counter is reset and starts from the same position.

[waclawek.jan]

Posted on October 13, 2017 at 10:14

Note, that in some newer STM32 families ('F7, 'L4) the SMS field of TIMx_SMCR has been extended (beware, the extra bit is 16th bit in TIMx_SMCR for backward compatibility!), and one extra mode has been added:

1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)

reinitializes the counter, generates an update of the registers and starts the counter.

Of course, this is *not* exactly the same as clearing counter at the *falling*edge of TRGI, so some of the effects (especially the corresponding compare/outputs' behaviour) are different, but for some other purposes this may be a fit.

JW