How does the DMA controller handle several streams simultaneously?

[arnold_w]

Posted on November 16, 2017 at 11:35

I am working with the stm32f4-discovery development board. An SPI bus configured in slave mode is using the DMA controller and I might add other things that will use the same DMA controller. This raises the question on how the DMA controller handles contention issues. When I think about it, the SPI slave should already create some 

contention because it is using 2 streams, one for Tx and one for Rx. How is this possible, how does the DMA controller manage to do 2 things at the same time? Even if I slow down my system clock to close to the SPI clock speed and disable the DMA controller FIFO, the SPI bus still works great. Can someone please shed some light on how the DMA controller handles several streams simultaneously?

[S.Ma]

Posted on November 16, 2017 at 11:52

You've got one data bus, so the DMA will run the read and write sequencially anyway, and the peripheral will go-on.

For the SPI, it's a non issue: You write SPI.DR before sending the data to the bus, and you get the SPI.DR as incoming byte when it is done. Both events don't come at the same time.