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pic_micro
Associate III
November 2, 2014
Question

How Disable global interrupt with ARM 32F0

  • November 2, 2014
  • 10 replies
  • 1786 views
Posted on November 02, 2014 at 08:15

Dear All

Following syntax does nit disable the global interrupt

Please advice 

uint32_t PriMask = 0x01;

//void __enable_irq (void);//Global Interrupt enable (using the instruction CPSIE i)

void __set_PRIMASK (uint32_t PriMask );// M0, M3PRIMASK = value// Assign value to Priority Mask Register (usingthe instruction MSR)

//void __disable_irq(void);

//void __diasable_irq(void);

//void __set_PRIMASK (uint32_t __set_PRIMASK);

//uint32_t  __get_PRIMASK(void)

It is seem to be ''PRIMASK;bit does not disable

please advice how disable PRIMASK BIT disable with CMSIS source code

Thanks in advance 

    This topic has been closed for replies.

    10 replies

    pic_micro
    pic_microAuthor
    Associate III
    November 2, 2014
    Posted on November 02, 2014 at 10:43

    Dear All,

    Following function do the thing

    __disable_irq()

    But I need to do it manually  using  PRIMASK bit 

    Tesla DeLorean
    Tesla DeLorean
    Guru
    November 2, 2014
    Posted on November 02, 2014 at 14:22

    Why?

    __get_PRIMASK(), and __set_PRIMASK() should allow you to check/set/clear bit 0
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    pic_micro
    pic_microAuthor
    Associate III
    November 3, 2014
    Posted on November 03, 2014 at 17:49

    Dear clivel

    Thanks for the reply

    I need to verify one more

    If I enable EXTI0  Line 0 interrupt ( PA0)

    Can I disable interrupt using ISER Register , if can which bit we need to set ISER register to disable Line 0 interrupt

    Please advice

    Tesla DeLorean
    Tesla DeLorean
    Guru
    November 3, 2014
    Posted on November 03, 2014 at 18:15

    Bit 5 of ICER one might presume from the documentation

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    pic_micro
    pic_microAuthor
    Associate III
    November 4, 2014
    Posted on November 04, 2014 at 16:50

    Dear clivel

    Yes it is working

    Grate Thanks for the reply

    It would be much appreciated, if you can give me a link of document that explaining each bit of ICER register

      

    Tesla DeLorean
    Tesla DeLorean
    Guru
    November 4, 2014
    Posted on November 04, 2014 at 17:14

    There's a one-to-one relationship with the IRQ#

    STM32F0308-Discovery_FW_V1.0.1\Libraries\CMSIS\Device\ST\STM32F0xx\Include\stm32f0xx.h 

    #if defined (STM32F0XX_MD) || defined (STM32F030X8)
/****** STM32F0XX_MD and STM32F030X8 specific Interrupt Numbers *************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
FLASH_IRQn = 3, /*!< FLASH Interrupt */
RCC_IRQn = 4, /*!< RCC Interrupt */
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
TS_IRQn = 8, /*!< TS Interrupt */
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 15, /*!< TIM2 Interrupt */
TIM3_IRQn = 16, /*!< TIM3 Interrupt */
TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
TIM14_IRQn = 19, /*!< TIM14 Interrupt */
TIM15_IRQn = 20, /*!< TIM15 Interrupt */
TIM16_IRQn = 21, /*!< TIM16 Interrupt */
TIM17_IRQn = 22, /*!< TIM17 Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
CEC_IRQn = 30 /*!< CEC Interrupt */
#elif defined (STM32F0XX_LD) || defined (STM32F030X6)
/****** STM32F0XX_LD and STM32F030X6 specific Interrupt Numbers *************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
...

    http://www.st.com/web/en/resource/technical/document/reference_manual/DM00091pdf

    Interrupt and exception vectors, Table Vector table
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    Tesla DeLorean
    Tesla DeLorean
    Guru
    November 4, 2014
    Posted on November 04, 2014 at 17:22

    Might want to review also ST's Cortex-M0 programming Manual

    http://www.st.com/web/en/resource/technical/document/programming_manual/DM00051352.pdf

    http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf

    ,

    http://www.amazon.com/The-Definitive-Guide-ARM-Cortex-M0/dp/0123854776

    (s)
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    pic_micro
    pic_microAuthor
    Associate III
    November 4, 2014
    Posted on November 04, 2014 at 17:51

    Thanks

    It is clear 

    As per this table we can't manage every individual pin of each port. and we can only grouping pins

    Example

    7  EXTI4_15 EXTI Line[15:4] interrupts

    Tesla DeLorean
    Tesla DeLorean
    Guru
    November 4, 2014
    Posted on November 04, 2014 at 18:15

    As per this table we can't manage every individual pin of each port. and we can only grouping pins Example 7  EXTI4_15 EXTI Line[15:4] interrupts

    But the peripheral will let you manage them. The core by design only supports 32 external sources, where external means outside the core, not the chip.

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    pic_micro
    pic_microAuthor
    Associate III
    November 9, 2014
    Posted on November 09, 2014 at 05:37

    Dear clivel,

    Thanks for the advice

    Now I need to study after 10 times interrupted by TIM2 the CMU goes to sleep mode

    Please give some hints with source codes

    void power(){

     PWR->CR |= PWR_CR_PDDS;

    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    }

    Thanks in advance

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