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How can I prevent shared ISR from triggering the opposite core?

Associate III


I have a dual core project on an STM32H745. Timer 8 is used by the CM7, Timer 13 is used by the CM4. Timer 8 and Timer 13 share an IRQ, "TIM8_UP_TIM13_IRQHandler".

I've double checked the setup and:

CM7 RCC_C1_APB2ENR has TIM8 set and RCC_C1_APB1LENR has TIM13 clear.

CM4 RCC_C2_APB2ENR has TIM8 clear and RCC_C2_APB1LENR has TIM13 set.

TIM13 gets started by the CM4 early on in the code. TIM8 has not yet been started on the CM7. However, I end up in the ISR on the CM7. On entry to the ISR running on the CM7 I notice the following:

CM7 TIM8 UIE is clear (although UIF is set - but I cleared that and the ISR still happens).

CM4 TIM13 UIE and UIF are both set, so the interrupt seems to be coming from there.

It appears to me that because the interrupt is shared and one of the interrupt sources are requesting attention, that both cores will enter the ISR. I would have thought the IRQ was gated by whether that peripheral was enabled to that core?

Anyone else experienced this? Is this really what happens, or is it more likely that I've screwed something elsewhere?

Is there any way to stop this, other than just avoiding this kind of mixed sharing of ISRs? Because at the minute I'm wasting time in an ISR that does nothing on the CM7 and if the CM4 doesn't service it quickly enough the CM7 gets locked into an ISR handling loop.