2013-09-20 06:40 PM
TIM2->
EGR
|= TIM_EGR_UG
) is meant to be updating the flag every time the Counter reaches ARR value. I really don't seems to see why it isn't working can someone help me? Many Thanks again Regards Entropy/*
Timer ISR running on STM32F407VG with COIDE Please ignore the comments were meant for other development code. Thanks*/
#include<stdint.h>
#include<stdlib.h>
#include <stdbool.h>
#include''stm32f4xx.h''
#include''stm32f4xx_rcc.h''
#include''stm32f4xx_tim.h''
#include''stm32f4xx_gpio.h''
#include''core_cm4.h''
volatile bool Process_Task = false;
void _delay_us(uint32_t us);
void _delay_ms(uint32_t ms);
void
TIM2_IRQHandler(
void
);int main()
{
SystemInit();
GPIO_InitTypeDef
GPIO_InitStructure; GPIO_InitStructure;RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD,
ENABLE
);RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM3,
ENABLE
);GPIO_InitStructure.
GPIO_Pin
= GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;GPIO_InitStructure.
GPIO_Mode
=
GPIO_Mode_OUT
;GPIO_InitStructure.
GPIO_OType
=
GPIO_OType_PP
;GPIO_InitStructure.
GPIO_Speed
=
GPIO_Speed_100MHz
;GPIO_InitStructure.
GPIO_PuPd
=
GPIO_PuPd_NOPULL
;GPIO_Init(GPIOD, &GPIO_InitStructure);
NVIC_InitTypeDef
NVIC_InitStructure;/* Enable the TIM2
gloabal
Interrupt */ NVIC_InitStructure.NVIC_IRQChannel
=
TIM2_IRQn
;NVIC_InitStructure.
NVIC_IRQChannelPreemptionPriority
= 0;NVIC_InitStructure.
NVIC_IRQChannelSubPriority
= 1;NVIC_InitStructure.
NVIC_IRQChannelCmd
=
ENABLE
;NVIC_Init(&NVIC_InitStructure);
/* TIM2 clock enable */
TIM2->
PSC
= 41999;TIM2->
ARR
= 3999;TIM2->
CNT
= 0;TIM2->
EGR
|= TIM_EGR_UG;TIM2->
SR
&= ~ TIM_SR_UIF;TIM2->
CR1
|= (TIM_CR1_OPM);
// Clear the update flagTIM2->
DIER
|= TIM_DIER_UIE;
// Enable interrupt on update eventNVIC_EnableIRQ(
TIM2_IRQn
);
// Enable TIM6 IRQTIM2->
CR1
|= TIM_CR1_CEN; // Enable TIM6 counter//while (!(TIM2->SR & TIM_SR_UIF));
while
(1){
GPIOD->
ODR
^= 1<<13; _delay_ms(100);}
}
void
TIM2_IRQHandler(
void
){
if
(TIM2->
SR
& (TIM_SR_UIF))// If update flag is set
{ {
GPIOD->
ODR
^= 1<<15; TIM2->SR
&= ~TIM_SR_UIF;
//Clear it. //Process_Task = true; // Set D15 high// GPIOD->ODR |= 1<<15; // Interrupt has been handled
//_delay_ms(15);
}
//delay_ms(15);
}
void _delay_us(uint32_t us)
{
TIM3->
PSC
= 83 ;
TIM3->
ARR
= us -1TIM3->
CNT
= 0;TIM3->
EGR
|= TIM_EGR_UG;TIM3->
SR
&= ~ TIM_SR_UIF;TIM3->
CR1
|= (TIM_CR1_OPM);
// Clear the update flagTIM3->
CR1
|= TIM_CR1_CEN;while
(!(TIM3->
SR
& TIM_SR_UIF));}
void _delay_ms(uint32_t ms)
{
while
( ms -- > 0) {_delay_us(1000);
}
}
2013-09-30 06:20 AM
And what's that testing? Presumably a cheap way to test if a singular high order bit is high or low. Just test the bit directly.
The connectivity in both cases is not sufficiently clearly stated to make much of a determination.