2020-06-10 04:17 AM
2020-06-10 06:17 AM
A delay between bytes is typically not an issue for SPI communication.
To remove it, you could send using DMA, or slow down you clock speed.
2020-06-10 07:12 AM
Although the STM32F4 series SPI controller has no FIFO, there is still a single data unit worth of buffer. If SPI is idle and data is written into SPIx->DR, it is immediately transferred to the internal shift register, TXE status is set, and DR can be written once more. If the software manages to write new data into DR before the previous one is completely shifted out, there should be no delay.
In the typical clock configuration the SPI bitrate is 1/4 of the core clock, so when using 16 bit frames the software has 64 cycles to update the DR register. This can be achieved in a software loop, or using DMA, but it would need a very tightly optimized interrupt handler.
It is not worth setting up a DMA channel for transmitting 2x16 bits, you can just write the data register two times, checking TXE between them. Unless an interrupt happens exactly after you write DR the first time, there should be no delay.
Of course if you are using some library instead of writing the registers directly, the story is quite different.