2015-04-18 02:12 PM
I can't figure out the cause of the Hard Fault:
Chip: STM32F405RG Instruction (gcc generated program): vldr s0, [r4] r4 contains an address in the main RAM and aligned (0x2....4) Stepping over it results in a jump to the HardFault handler, CFSR gets NOCP flag set (0xE000ED28 = 0x00080000). According to the memory inspector, CPACR has both CP10 and CP11 set to 0b11. What have I missed? What can I do? Are there more constrains to the VLDR instructions? Thank you in advance EDIT: VLDR is executed inside the USB_OTG_FS interrupt handler callstack In FPCCR LSPEN and ASPEN are set, LSPAC is 1 prior to VLDR execution. HFRDY and THREAD are set after VLDR execution/fault #stm32-nocp-cpacr-hardfault-fpu-v2015-04-18 04:19 PM
Hah! It seems not to happen if LSPEN is cleared. Could anyone explain why and how I could keep using LSPEN?