Hard fault problem

[markmark9122]

Posted on June 10, 2014 at 16:34

For several years I have developed software for an STM32F103 target using Eclipse/OpenOCD/Olimex ARM-USB-OCD. Recently my hard drive failed so I replaced it and re-installed everything. My project will not now run, and I have located the problem as follows:

After a reset the code ensured the RCC is set to the internal 8MHz RC clock:

0x08001e26: InitRCC+46 ldr r3, [pc, #560]
0x08001e28: InitRCC+48 ldr r2, [r3, #0]
0x08001e2a: InitRCC+50 ldr r3, [r2, #4]
0x08001e2c: InitRCC+52 bfc r3, #0, #2
0x08001e30: InitRCC+56 str r3, [r2, #4]

At line 2, r2 is loaded with 0x40021000 (RCC clock). At line 3, r3 is loaded from address 0x40021 The code then proceeds to enable the prefetch buffer in preparation for setting flash latency then selecting a crystal clock:

0x0800088c: InitFlash+8 ldr r3, [pc, #84]
0x0800088e: InitFlash+10 ldr r3, [r3, #0]
0x08000890: InitFlash+12 ldrb r2, [r3, #0]
0x08000892: InitFlash+14 orr.w r2, r2, #16
0x08000896: InitFlash+18 strb r2, [r3, #0]

At line 2, r3 is loaded with 0x40022000. At line 3 r2 should be loaded with the contents of 0x40022000 (ACR). Instead the processor vectors to the hard fault exception. This suggests that register 0x40022000 is not used, yet it is, and register 0x40021004 works correctly. Can anyone explain why? The problem is particularly frustrating since all works correctly before my hard drive failed. The code has not changed, and as far as I am aware all applications and drivers are the same. #hard-fault

[Tesla DeLorean]

Posted on June 10, 2014 at 17:01

Hard to guess without some more context and source.

The prefetch is going to choke if the wait states are wrong, and the core fetches garbage. The switch to HSI will fail if the HSI is not on/ready? You'd want to dump out the register content at the fault, and see if they have the values they should have. The disassembly is too one dimensional for me to see anything. Model code after STM32F10x_StdPeriph_Lib_V3.5.0\Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c

[markmark9122]

Posted on June 11, 2014 at 01:04

I just spotted the problem myself:

In the second code extract the compiler generated the byte read instruction ldrb instead of the word read ldr.  The STM32 obviously doesn't like bye reads of ACR.  When I tweaked the compiler all worked well.