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RMcCa
RMcCa
Senior II
July 12, 2020
Question

H745 DMA hardware problem?

  • July 12, 2020
  • 4 replies
  • 1292 views

I have encountered a strange problem with some of the dmas seeming to not ​be able to write to GPIOD ODR. I am using 5 dmas in a chain to write 16bit data to port D. Initially, i was using dma1 streams 0-4 but noticed that the signal was correct for streams 0,1 & 4 but high (logic 1) when streams 2&3 were active. After alot of trial and error and debugging I wrote code that that configured all 16 dma streams identically and tried them all. The results are the streams 0,1,2,4 & 5 for both dmas work as expected while the others appear to work (debugger shows correct register data before/after transmission) but don't write anything to the odr. I hate to be one of those people that tries to blame a hardware problem on faulty software, but this has got me stumped.

My code appears to work fine using dma1 streams 0, 1, 2, 4 and dma2 stream 0, but why? Again, i found that with 16 identically configured dma streams that all of them work from the software perspective but only 10 drive the port d odr correctly.​

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4 replies

RMcCa
RMcCaAuthor
Senior II
July 12, 2020

I forgot to mention that i am using simple C code and the register interface. The only hal in my code is the clock config in the f7 code.

I am using the capture event(falling edge) of a gated timer to trigger the dma and the ca​pture event interrupt of the master timer to enable the dmas in a chain using a simple state machine.

TDK
TDK
July 12, 2020

Can you present a minimal working example which shows the problem?

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RMcCa
RMcCaAuthor
Senior II
July 12, 2020

I got the stream numbers mixed up in the op. Streams 0,1,4 and 5 work with both dmas while the others don't.

I on my phone at the moment, but i am writing the same values to the cr, par, ndtr and moar of each stream. The source is a 6 element half word array, alternating 0 and 0xffff. The slave timer makes 6 edges during the gate time and all 5 dmas always ​have ndtr = 0 after a complete cycle whether it drove the odr or not. I set all the dmamux selects in advance to tim3 capture, but am careful that only 1 dma is enabled at a time.

It is interesting that the trouble is with alternating pairs and both dmas act the same.​

TDK
TDK
July 12, 2020

The ones that work are 0, 1 modulo 4. Suggests maybe you're messing up the correct byte or bit position to check for flags. I can't believe that this is a hardware problem.

If you show your code, I will test it out. Don't really want to code this to confirm as it's probably a software problem.

> I am using 5 dmas in a chain to write 16bit data to port D.

So you're writing to ODR with multiple streams at the same time? They're going to overwrite one another. It's probably better to write to BSRR instead.

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RMcCa
RMcCaAuthor
Senior II
July 12, 2020

Sometimes one just needs alittle help. I am not testing any of the dma flags in my code, but was only writing 16 bits to the dma flag clear registers. Problem solved!

Thanks​.

I am developing a multiprocessor(5) 16 bi​t spi like data bus were each processor will drive it's newest data on the bus in turn while the other 4 listen. Instead of reconfiguring a single dma each time, i thought it faster and simpler to use 5 dmas in turn. That way i can set the direction and ntdr in advance of the data bus cycle. Only one is enabled at a time.

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