H743 PLL1 P-divider discrepancy

[DanielST]

Hi!

I wonder if the P-divider for the PLL1 on the STM32H743 is allowed to be 1.

The reference manual (rev. 8 ) states in figure 47 (section 8.5.5) that only values from 2, 4, ... to 128 are allowed.

In the register description (section 8.7.13) however, a divider of 1 corresponding to a register value of 0 is also listed as valid.

Which one is correct?

Kind regards

[Tesla DeLorean]

In most implementations the VCO is a pulse generator where as the MCU wants a 50/50 duty cycle as it uses both edges of the clock

[LCE]

Mind what they are talking about: divider value or register value.

For STMH723 the DIVP1 register values must be odd, because the divider value = DIVP1 + 1.

So the divider value is 1 or even, with the register value DIVP1 being 0 or odd.

So read both description and register carefully, in case of doubt trust the register description.
Or simply try... :D

[DanielST]

I work with the STM32H723 as well but there the reference manual is consistent, explicitly allowing DIVP = 1.

The thing is, even the register description is inconsistent. It states "Note that odd division factors are not allowed." but then directly lists the case for a division by 1 (I now added screenshots from the reference manual above).

I tried it as well and seems to work but it would be nice to have it confirmed.

[Tesla DeLorean]

Not sure what the argument is here.

x is the PLL number, not the divisor

It says DIVP1 (PLL1) needs to be even, but DIVP2 (PLL2), DIVP3 (PLL3) is more flexible.

The MCU, using the P-tap of PLL1, needs a 50/50 duty clock so it can't be 66/33, 80/20 or 1/99 without that having repercussions wrt critical paths deep in the design. The MCU uses both phases of the clock. This is why it doesn't want ODD divisors here.. Not sure the reasoning is baffling.

Now other peripherals might be more tolerant, especially if they basically DIV2 or function on a single clock edge, and not both. I'll note that peripherals needing DDR/DTR typically want a clock that's twice as fast going in, so DSI wanting a 250 MHz DDR signal, will want a 500 MHz clock.

Why is it done like this? Because they want to design and characterize the "cell" once, and then drop 3 instantiations on the same thing, and not design and test 3 different cells. They then give you "rules of use" so you don't break down stream circuits with assumptions they've made by setting inappropriate values.

Ask your FAE, or post via Online Support Request Ticket.

[DanielST · Accepted solution]

I apparently did something wrong with my previous testing, a divider of 1 does not seem to work (contrary to what is stated in the register description). 

This is also interesting because the reference manual states that the divider should be set to 1 (register value 0) when a PLL output is not used. This is apparently not possible for the PLL1 P-divider.