H743 PB4 defaults to a high level issue.

奥特曼9527 · ‎2025-06-19

When Pb4 is reset, it is at a high level. Can't this be configured in the hardware? It's too disgusting. The PCB has been designed and encountered this pit.

Andrew Neil · ‎2025-06-19

PB4 is NRST - it's active low, so you'd expect its default state to be high.

This power-up state is clearly documented:

https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=533

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

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Andrew Neil · ‎2025-06-19

PB4 is NRST - it's active low, so you'd expect its default state to be high.

This power-up state is clearly documented:

https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=533

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

TDK · ‎2025-06-19

In addition to @Andrew Neil 's comments: no, it cannot be configured in hardware. An external pulldown could help here.

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奥特曼9527 · ‎2025-06-19

How many resistors are suitable for external pull-down? I don't know what is suitable for internal pull-up,

奥特曼9527 · ‎2025-06-19

I know what you're saying, but it's frustrating to see that such high-end chips don't have internal settings. It's common for us to use MCU to control IO high and low levels, and this kind of setting makes users make mistakes. I think it's not just me, many users have used it before.

Andrew Neil · ‎2025-06-19

If you pull NRST low, that will keep the microcontroller in reset - it will never start!

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

Andrew Neil · ‎2025-06-19

@奥特曼9527 wrote:
it's frustrating to see that such high-end chips don't have internal settings.

Do you know of any chips which do have such settings?

It's a standard part of the design process to understand what the power-up state of the IOs will be, and design the rest of the circuit accordingly.

You should be able to find the (approximate) value of the internal pullup in the datasheet.

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

奥特曼9527 · ‎2025-06-19

This is already such a bad design for 2025 that I am very concerned about ST's leadership position.

TDK · ‎2025-06-19

You're being dramatic. There are a very limited number of IO pins that have non-floating status at reset. There are good reasons why (so chip isn't bricked). Yes, you need to learn which ones they are so you are not bit by this. But it's been in the chips for 20+ years. I don't think ST will live or die by that decision.

If you feel a post has answered your question, please click "Accept as Solution".

Andrew Neil · ‎2025-06-19

So, again, who do you see with chips which do have this feature?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.