general purpose TIMx compare and interrupt

[guyvo67]

Posted on August 31, 2009 at 12:20

general purpose TIMx compare and interrupt

[guyvo67]

Posted on May 17, 2011 at 13:21

Hi,

Some general info first: (PLL on 72MHz -> 10ms) TIM_TimeBaseStructure.TIM_Period = 9999; TIM_TimeBaseStructure.TIM_Prescaler = 72; ( preload on ) TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable); ( no output pins -> made by ints ) TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Inactive; I use the compare match together with interrupts on my general purpose timers. I have all CC1-4 enabled. Works fine but still one thing that bothers me though. My timer has a window of 0-10000 µs. If I lay my OCx(pulse) in that interval al works correctly. But if I assign OCx a value greater than the 10ms ( eg 0XFFFF )of my timer I would expect no interrupts because there are no matches at all. I saw that the behaviour of that is some how random but I get interrupts. I tried to look into the rm0008 but found no example nor explanation on this. Also putting the OCx on zero triggers an interrupt but this could be logic because of the match with zero if timer resets. So what should be the exact behaviour of the interrupt in respect to the OCx match when value is greater than the actual timer period ? And is getting an interrupt normal when putting OCx at zero ? Guy

[guyvo67]

Posted on May 17, 2011 at 13:21

To return on the subject I inspected the cortex register description in more detail and in the description of:

TIM1/TIM8: TIMx_CCR1 If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. TIMx_SR Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode)TIM2/3/4/5: TIMx_CCR1 If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. TIMx_SR CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register. 1. I can only read something on my subject of having CCR1>ARR within the TIM1/8 description. This is not mentioned in general purpose timer description so can I assume that this behavior counts for all timers using the compare match ? 2. And what can be considered as an “update event occurs � -> overflow ? compare & match ? because somewhere it’s mentioned that the compare match does not depend on UPD events. Guy