FSMC clock signal at higher frequencys

[thecrocodial]

Posted on June 15, 2014 at 13:45

Hi,

I am trying to control a TFT over LVDS with an STM32F429. At around 30 MHz the Signal seems to be ok, but the Display wants at least 40MHz. Turning up the Speed above ~33Mhz is messing up the clock signal and visible errors occur. The datasheet says it should work with up to 42MHz. Is there a chance to get a clean 42Mhz signal by following some Layout rules or adding some components (until now i added a resistor and a capacitor, that got me up to 33Mhz) or should i switch to another controller?

[stm322399]

Posted on June 15, 2014 at 14:00

GPIO have settings to control output speed (slope rate control), did you take care to set all fast lines to support at least 50MHz.

-- laurent

[thecrocodial]

Posted on June 15, 2014 at 14:23

yep everything set to max

[stm322399]

Posted on June 15, 2014 at 14:33

What about compensation cell setting ?

[thecrocodial]

Posted on June 15, 2014 at 15:38

i didn't know it existed, i will read some more about it, thank you!

[Tesla DeLorean]

Posted on June 15, 2014 at 17:07

How are you viewing the signal? If you are using a 1X/10X scope probe, make sure it's in 10X mode

[thecrocodial]

Posted on June 18, 2014 at 12:27

The probe is on 10x. Activating cell compensation did not help. I built an adapter for the 429 Discovery board to check if my own STM32 Board had major flaws before the LVDS part, but the result was the same - output is fine until ~33MHz and then gets worse the higher you go ( starts with image jumping, total running mess @40MHz ).

[thecrocodial]

Posted on June 18, 2014 at 16:39

turns out that the limiting factor is the external sdram. will post if i find anything interesting.