FSMC clobbers I2C1

[brianforde9]

Posted on February 16, 2009 at 08:09

FSMC clobbers I2C1

[brianforde9]

Posted on May 17, 2011 at 12:43

I am using STM32F103ZET.

Is there any reason why I2C1 should stop functioning when I enable FSMC? I am using the default pinout (PB6 & PB7) for I2C1 (i.e. not remapped). . . . /* I2C1 functions correctly */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE); /* I2C1 does not function */ . . . Brian F.

[jaroslaw2]

Posted on May 17, 2011 at 12:43

Hi,

This library works like that. Set all clocks at once, this is what I usually do.

Code:

/* All clocks are defined hire */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3 | RCC_APB1Periph_TIM4 |RCC_APB1Periph_TIM2, ENABLE);

[brianforde9]

Posted on May 17, 2011 at 12:43

Jaroslaw,

Makes no difference. Whether I enable all, or single module, enabling the FSMC clobbers I2C1. Brian F.

[jaroslaw2]

Posted on May 17, 2011 at 12:43

Did you check the errata sheet?

Quote:

FSMC with I2C1 and TIM4_CH2 Description When the FSMC is being used, the NADV signal is set to 1 by default when the alternate function output is selected for this pin. TIM4_CH2 and the I2C1 SDA signal are in conflict with the NADV signal. Workaround Do not use TIM4_CH2 when the FSMC is being used. Concerning I2C1, it is possible to use the remap functionality available on the PB8 and PB9 pins.

[brianforde9]

Posted on May 17, 2011 at 12:43That's possibly the problem I'm encountering. Thanks.

[jj]

Posted on May 17, 2011 at 12:43

Like you - we have been guilty of ignoring/paying inadequate attention to errata. Not the best practice...

Further - errata are the, ''known, verified & admitted'' faults. We can't take full comfort because our desired feature/behavior is not ''errata-listed.'' Independent testing/confirmation - under the closest possible match to one's final operation/conditions - is our safest course. While unexpected - and disappointing - the chip's inability to deliver ALL features - under ALL operating modes - is hardly unique. Feature-cram, tight design schedule, and price pressure are the likely villains.

[tibo]

Posted on May 17, 2011 at 12:43

The FSMC is using PB7 for the NADV signal. But NADV is not used for NAND or

SRAM and it is not used for NOR flash without multiplexed address/data bus (see Reference Manual (RM0008), page 368), so the temperature sensor will probably work on the Eval Board. Here are more infos:

http://www.st.com/mcu/forums-cat-7268-23.html

[virtualfight]

Posted on May 17, 2011 at 12:43

On the STM3210E-Eval Board there is a I2C temperature sensor, wich is connected to PB6 and PB7 and the demo application uses the I2C1 and the FSMC at the same time, doesn't it? So how is it possible?

[ccowdery9]

Posted on May 17, 2011 at 12:43

OK, if you look at the source for the demo code for the STM3210-E, you can see a software fix.

Look in tsensor.c, in function Thermometer_Temperature(void) You will see that there is lots of FSMC activity, mainly turning the FSMC clock on & off! So I guess that is the fix if you need to use IIC & FSMC, turn off FSMC, initialise & use IIC, then turn FSMC back on again........ I will try it out myself now. Chris.