FMC SRAM High Speed problem

[cleanser23]

Posted on March 06, 2015 at 20:29

I'm using Keil on an stm32f4xx with 10ns read/write sram

I have configured the FMC with a data ready of 2 HCLK (my speed is 180 Mhz) so that is 90 Mhz, which is slower than the rating of 100 Mhz of the SRAM, however the FMC will not read/write the sram correctly unless it is set to a data ready delay of 3 instead of 2 (60 Mhz)I have enabled the compensation cell and set all GPIO clocks associated with the FMC to high, what could cause this?The speed isnt high enough for length matching to be an issue, nor should the Z0 cause a problem (it is around 60 Ohms, close enough to 50), any tips?

[waclawek.jan]

Posted on March 06, 2015 at 21:12

No high-speed oscilloscope, or LA around?

Any link to the SRAM's datasheet? Are you talking about the FMC_BTRx.DATAST parameter, and in Mode1? What happens if you change the pins' speed settings to 50MHz? What VDD are you running at? Do you have solid grounds and decent VDD decoupling? Is the problem with read or write? You can possibly separate the two using a split-timing mode (FMC_BCRx.EXTMOD = 1). JW

[cleanser23]

Posted on March 07, 2015 at 16:58

We have an Oscope, it shows it running fine at 60 Mhz, I'll do it with both and take pictures soon.

http://www.issi.com/WW/pdf/61WV102416ALL.pdfSRAM data sheetThat is the parameter I'm talking about I'm not sure why changing from 100 Mhz to 50 Mhz would be better but I'll tryI am running 3.3 VDD and have 100 nF on every VDD and 2 4.7 uF decoupling those, and 220 uF decoupling the board (followed reccomended setup and then some, I doubt this is the problem) I also have an internal ground plane and am running off a test PSU atm so I would see if I dip and brown out or anything of that sort.The problem is with both read and write, I'll post what I see on the debugger at the same time as all the othersSorry for not having answers to all your suggestions, I am not in lab right now and won't be again until monday, but as soon as I am I'll get you all those answers and photos, thanks a ton for your help

[waclawek.jan]

Posted on March 07, 2015 at 19:12

With these things, I always need to make a couple of drawings, based on what is in the datasheets, and then distinguish what is ''granted'' and what is ''expected''.

For example, when reading, the mcu expects the data be valid min. tsu(Data, NE) = THCLK+2.5ns before the trailing (rising) edge of FMC_NE (= /CE), and the memory grants that data will be output max tACE=10ns after the leading (falling) edge of /CE. That with THCLK=1/180MHz=5.6ns gives me min. 18.1ns NE low, which means that even DATST=3 might not suffice for unconditional reliability. You might want to repeat the exercise for other parameters, and for write. JW

[cleanser23]

Posted on March 08, 2015 at 22:50

Thanks for the reply!

I'm sorry but I can't find in the datasheet or the reference manual where it says that it needs a 2.5 ns setup time as well as the number of THCLK, can you tell me where that information is?

[cleanser23]

Posted on March 08, 2015 at 23:04

Found it where it belongs, in the datasheet under FMC timings, this makes sense, glad my SRAM isn't just malfunctioning!  I wish I could run faster, but that's life!

[ajacquet]

Posted on March 10, 2015 at 00:54

Hello all ,

If you are using the new cube library , you be able to tell show me the setup for the gpio and the sram configuration???  Been beating my head over this for the past two weeks here without success  in getting the address port to do anything .... Also how to write to and address port the new way too and the old way isn't working.....