Fastest memory-to-memory (actually to/from GPIO) DMA using STM32H562VI

[Dave_E_Mason]

I am new to this forum and to STM32CubeIDE.I am working with a NUCLEO-H563ZI board.

Where can I find how to decide the best Timer to use for my DMA?

The top priority for my project is to set up DMA to do 3 things simultaneously as fast as possible for a specified quantity of words transferred.

1. Output from one memory buffer to one GPIO port - only 8 bits actually needed. 

2. Input to another memory buffer from another GPIO port - 12bits from an ADC

3. Output to the ADC clock via a GPIO pin. AFAIK the LTC2228 ADC will change the data on the ADC's GPIO port during the rising edge of this clock.

I am unclear whether each data access will take 6, 5, or 4 cycles of the 250MHz MCU clock.

[TDK]

Code it up and increase the speed until something fails. I would guess it will fail somewhere in the 10MHz range.

It won't depend on the timer used, it will depend on the speed and contention of the memory buses within the CPU.

[Tesla DeLorean]

The GPIO registers aren't 8-bit wide, do the transaction via GPIO->ODR as 16-bit or GPIO->BSRR as 32-bit. Some STM32 will fail if the widths are wrong, can't speak to the H5 specifically. Pick a DMA unit with proximity to the GPIO peripheral, ideally with memory that's as closely coupled as possible, and not in general usage.

A speed of 8 - 10 MHz might be realistic. I seem to recall the mechanics of the F4 yielded 21 MHz patterns, but the designs have since been "complicated" and "improved"..  YMMV

[MasterT]

I think the same, unlikely speed gets over 5 MHz, architecture of the uCPU is too complex: different domains, busses/bridges, dma latence etc.

You can get higher sampling rate using internal ADC's, if there are a few of them

[Dave_E_Mason]

I was expecting all transactions to be 32-but, using GPIO->BSRR as you say.

I already get 20MSPS using a 120MHz STM32F205VGT6 but it's awkward to examine that firmware so I'm hoping (wrongly?) to start from scratch.