f427 accesses only part of SDRAM

[matthias239955_stm1]

Posted on January 05, 2016 at 02:42

Hello all,

I am new around here; please excuse in advance my probably boring query... I have a custom board with an STM32F427ZI together with 256Mb of SDRAM (the chip is an AS4C16M16S). I configured it with the code below (not understanding fully what I am doing). My problem is that I can access only the first 128KB after address 0xD0000000. If I go past this point it HardFaults, (or read only zeroes depending on the particular configurations I tried). Could a good soul take a look at the code, and/or hint at a direction where to go?<pre>  FMCT.FMC_LoadToActiveDelay      = 2;                         //  2   1 clock cycle = 1 / 90MHz = 11ns  FMCT.FMC_ExitSelfRefreshDelay   = 6;                         //  6   TXSR: min=66ns  (  6x11ns)  FMCT.FMC_SelfRefreshTime        = 4;                         //  4   TRAS: min=44ns  (  4x11ns) max = 120k (ns)  FMCT.FMC_RowCycleDelay          = 6;                         //  6   TRC:  min=66ns  (  7x11ns)  FMCT.FMC_WriteRecoveryTime      = 2;                         //  2   TWR:  min=1+7ns (1+1x11ns)  FMCT.FMC_RPDelay                = 2;                         //  2   TRP:  20ns      (  2x11ns)  FMCT.FMC_RCDDelay               = 2;                         //  2   TRCD: 20ns      (  2x11ns)  FMCI.FMC_Bank                   = FMC_Bank2_SDRAM;              //  FMC SDRAM control configuration  FMCI.FMC_ColumnBitsNumber       = FMC_ColumnBits_Number_9b;     //  Row addressing   : [ 8:0]  FMCI.FMC_RowBitsNumber          = FMC_RowBits_Number_12b;       //  Column addressing: [11:0]  FMCI.FMC_SDMemoryDataWidth      = FMC_SDMemory_Width_16b;  FMCI.FMC_InternalBankNumber     = FMC_InternalBank_Number_4;  FMCI.FMC_CASLatency             = FMC_CAS_Latency_3;            //  CL: Cas Latency = 3 clock cycles  FMCI.FMC_WriteProtection        = FMC_Write_Protection_Disable;  FMCI.FMC_SDClockPeriod          = FMC_SDClock_Period_2;  FMCI.FMC_ReadBurst              = FMC_Read_Burst_Disable;  FMCI.FMC_ReadPipeDelay          = FMC_ReadPipe_Delay_1;  FMCI.FMC_SDRAMTimingStruct      = &FMCT;  FMC_SDRAMInit(&FMCI);                                           //  FMC SDRAM bank initialization  //  Configure a clock configuration enable command  FMCC.FMC_CommandMode            = FMC_Command_Mode_CLK_Enabled;  FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;  FMCC.FMC_AutoRefreshNumber      = 1;  FMCC.FMC_ModeRegisterDefinition = 0;  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET);  FMC_SDRAMCmdConfig(&FMCC);  for(timeout = 0x00; timeout < 0xD0000; timeout++) {}  //  Configure a PALL (precharge all) command  FMCC.FMC_CommandMode            = FMC_Command_Mode_PALL;  FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;  FMCC.FMC_AutoRefreshNumber      = 1;  FMCC.FMC_ModeRegisterDefinition = 0;  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));  FMC_SDRAMCmdConfig(&FMCC);  //  Configure a Auto-Refresh command  FMCC.FMC_CommandMode            = FMC_Command_Mode_AutoRefresh;  FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;  FMCC.FMC_AutoRefreshNumber      = 1;  FMCC.FMC_ModeRegisterDefinition = 0;  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));  FMC_SDRAMCmdConfig(&FMCC);  //  Configure a load Mode register command&sharpdefine SDRAM_BURST_LENGTH_1                ((uint16_t)0x0000)&sharpdefine SDRAM_BURST_LENGTH_2                ((uint16_t)0x0001)&sharpdefine SDRAM_BURST_LENGTH_4                ((uint16_t)0x0002)&sharpdefine SDRAM_BURST_LENGTH_8                ((uint16_t)0x0004)&sharpdefine SDRAM_BURST_TYPE_SEQUENTIAL         ((uint16_t)0x0000)&sharpdefine SDRAM_BURST_TYPE_INTERLEAVED        ((uint16_t)0x0008)&sharpdefine SDRAM_CAS_LATENCY_2                 ((uint16_t)0x0020)&sharpdefine SDRAM_CAS_LATENCY_3                 ((uint16_t)0x0030)&sharpdefine SDRAM_OPERATING_MODE_STANDARD       ((uint16_t)0x0000)&sharpdefine SDRAM_WRITEBURST_MODE_PROGRAMMED    ((uint16_t)0x0000)&sharpdefine SDRAM_WRITEBURST_MODE_SINGLE        ((uint16_t)0x0200)&sharpdefine SDRAM_MODEREG (SDRAM_BURST_LENGTH_2|SDRAM_BURST_TYPE_SEQUENTIAL|SDRAM_CAS_LATENCY_3|SDRAM_OPERATING_MODE_STANDARD|SDRAM_WRITEBURST_MODE_SINGLE)  FMCC.FMC_CommandMode            = FMC_Command_Mode_LoadMode;  FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;  FMCC.FMC_AutoRefreshNumber      = 1;  FMCC.FMC_ModeRegisterDefinition = SDRAM_MODEREG;  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));  FMC_SDRAMCmdConfig(&FMCC);  //  Set the refresh rate counter  //  (15.6 us x Freq) - 20 = (15.6 * 90MHz) - 20 = 1384  //  Set the device refresh counter  FMC_SetRefreshCount(1384);  while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET);

</pre>

#sdram

[Tesla DeLorean]

Posted on January 05, 2016 at 03:36

Please show the code that Hard Faults

[matthias239955_stm1]

Posted on January 05, 2016 at 12:41

Hello clive1, thanks for helping. I've read many of your post which were very helpful.

False alarm... I had spent so much time debugging SDRAM issue that it didn't occur to me that the problem could have come from somewhere else (which your message suggested). It now works perfectly fine!Sorry about this.

[Tesla DeLorean]

Posted on January 05, 2016 at 14:04

which your message suggested

Glad you caught that. No need to be sorry.