Posted on May 30, 2017 at 18:50Ethernet phys and switches.
I am wading into a n area that I know nothing about ethernet, in particualar, phys, and switches. Our board was previously setup tocomminicate with a phy chip, DP8384K. It took little set up beyond establishing the addresses and then it worked fine with out telnet sessions. Not so lucky with the MARVELL 88E6085 switch Ports 0-7 have phys, ports 9 and 10 do not so I am trying to communicate using the MII - PHY mode that the Marvell supportson port 10. Phy communication is being attempted using MDC/MDIO. Once reset is brouth high the 8 ports with phys work like a normal switch but I cannot yet get the STM32 to talk to it via MII. Sorry for this long winded explanation but ti brings me you a question that is perhaps generic enough to address this group.
Again, this is new territory for me so forgive the simple minded questions. In file stm32f4x7_eth.c there is a functon, uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue). Herein is seems the PHYAddress is shifted 11, the the registeris left shifted 6 and ORed into theMACMIIAR along with the write bit and busy bit. MACMIIDR gets the data value.
Is this a stardard configuration for all phy register writes? It seems this function on expects a control , register, and status register, and a status register offset. Yet the field mask is 0x7C which suggests 31 phy registers and this device seems to have many.
So my question is should I expect the ETH_WritePHYRegister() to manipulate all phy writes before sending them to SDIO, my chip seems to do quite a bit of manipulagtion itself beforehand. The bottom line is that I did not want to modify standard STM code.\\
Thanks,
jh
