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DMA - update timer pwm dutyCycle is working but if dma overflow back to 0 there are no values written

Makke.1
Associate II

‎2022-11-06 04:58 AM

I expect from DMA, squence 1000,0010,0100,0001

but I get out of my timer outputs:

1000,0010,0100,0001,0000

how to remove last "0000"

my code is:

main.c

extern DMA_HandleTypeDef hdma_tim1_ch1;

extern DMA_HandleTypeDef hdma_tim1_ch2;

extern DMA_HandleTypeDef hdma_tim1_ch3;

extern DMA_HandleTypeDef hdma_tim1_ch4_trig_com;

uint16_t speed = 10;

uint16_t speednew = 10;

uint16_t speed2;

uint16_t power;

uint16_t pwmss1[4];

uint16_t pwmss2[4];

uint16_t pwmss3[4];

uint16_t pwmss4[4];

void SystemClock_Config(void);

static void MX_GPIO_Init(void);

static void MX_DMA_Init(void);

static void MX_TIM1_Init(void);

static void MX_ADC1_Init(void);

static void MX_TIM3_Init(void);

int16_t out1;

int16_t out2;

int16_t out3;

int16_t out4;

   pwmss1[0] = 1000;

   pwmss1[1] = 0;

   pwmss1[2] = 0;

   pwmss1[3] = 0;

   pwmss2[0] = 0;

   pwmss2[1] = 0;

   pwmss2[2] = 1000;

   pwmss2[3] = 0;

   pwmss3[0] = 0;

   pwmss3[1] = 1000;

   pwmss3[2] = 0;

   pwmss3[3] = 0;

   pwmss4[0] = 0;

   pwmss4[1] = 0;

   pwmss4[2] = 0;

   pwmss4[3] = 1000;

 HAL_TIM_PWM_Start_DMA(&htim1, TIM_CHANNEL_1, (uint32_t *)pwmss1, 4);

 HAL_TIM_PWM_Start_DMA(&htim1, TIM_CHANNEL_2, (uint32_t *)pwmss2, 4);

 HAL_TIM_PWM_Start_DMA(&htim1, TIM_CHANNEL_3, (uint32_t *)pwmss3, 4);

 HAL_TIM_PWM_Start_DMA(&htim1, TIM_CHANNEL_4, (uint32_t *)pwmss4, 4);

 speed2 =65000;

 power = 0;

 /* USER CODE END 2 */

 /* Infinite loop */

 /* USER CODE BEGIN WHILE */

 while (1)

 {

    TIM3->CCR4 = power;

    TIM1->PSC = speed2;

    out1 = HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_8);

    out2 =HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_9);

    out3 =HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_10);

    out4 =HAL_GPIO_ReadPin(GPIOA, GPIO_PIN_11);

 }

}

/**

 * @brief System Clock Configuration

 * @retval None

 */

static void MX_TIM1_Init(void)

{

 /* USER CODE BEGIN TIM1_Init 0 */

 /* USER CODE END TIM1_Init 0 */

 TIM_MasterConfigTypeDef sMasterConfig = {0};

 TIM_OC_InitTypeDef sConfigOC = {0};

 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};

 /* USER CODE BEGIN TIM1_Init 1 */

 /* USER CODE END TIM1_Init 1 */

 htim1.Instance = TIM1;

 htim1.Init.Prescaler = 720;

 htim1.Init.CounterMode = TIM_COUNTERMODE_UP;

 htim1.Init.Period = 1000;

 htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;

 htim1.Init.RepetitionCounter = 0;

 htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;

 if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)

 {

   Error_Handler();

 }

 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;//updated was reset

 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;

 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)

 {

   Error_Handler();

 }

 sConfigOC.OCMode = TIM_OCMODE_PWM1;

 sConfigOC.Pulse = 0;

 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;

 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;

 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;

 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;

 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;

 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)

 {

   Error_Handler();

 }

 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)

 {

   Error_Handler();

 }

 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)

 {

   Error_Handler();

 }

 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)

 {

   Error_Handler();

 }

 sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;

 sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;

 sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;

 sBreakDeadTimeConfig.DeadTime = 0;

 sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;

 sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;

 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;

 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)

 {

   Error_Handler();

 }

 /* USER CODE BEGIN TIM1_Init 2 */

 /* USER CODE END TIM1_Init 2 */

 HAL_TIM_MspPostInit(&htim1);

}

/**

 * Enable DMA controller clock

 */

static void MX_DMA_Init(void)

{

 /* DMA controller clock enable */

 __HAL_RCC_DMA2_CLK_ENABLE();

 /* DMA interrupt init */

 /* DMA2_Stream1_IRQn interrupt configuration */

 HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 1, 0);

 HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);

 /* DMA2_Stream2_IRQn interrupt configuration */

 HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 1, 0);

 HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);

 /* DMA2_Stream4_IRQn interrupt configuration */

 HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 1, 0);

 HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);

 /* DMA2_Stream6_IRQn interrupt configuration */

 HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 1, 0);

 HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);

}

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Makke.1
Associate II

‎2022-11-06 05:12 AM

void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)

{

 if(htim_pwm->Instance==TIM1)

 {

 /* USER CODE BEGIN TIM1_MspInit 0 */

 /* USER CODE END TIM1_MspInit 0 */

   /* Peripheral clock enable */

   __HAL_RCC_TIM1_CLK_ENABLE();

   /* TIM1 DMA Init */

   /* TIM1_CH1 Init */

   hdma_tim1_ch1.Instance = DMA2_Stream1;

   hdma_tim1_ch1.Init.Channel = DMA_CHANNEL_6;

   hdma_tim1_ch1.Init.Direction = DMA_MEMORY_TO_PERIPH;

   hdma_tim1_ch1.Init.PeriphInc = DMA_PINC_DISABLE;

   hdma_tim1_ch1.Init.MemInc = DMA_MINC_ENABLE;

   hdma_tim1_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

   hdma_tim1_ch1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

   hdma_tim1_ch1.Init.Mode = DMA_CIRCULAR;

   hdma_tim1_ch1.Init.Priority = DMA_PRIORITY_LOW;

   hdma_tim1_ch1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

   if (HAL_DMA_Init(&hdma_tim1_ch1) != HAL_OK)

   {

     Error_Handler();

   }

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_CC1],hdma_tim1_ch1);

   /* TIM1_CH2 Init */

   hdma_tim1_ch2.Instance = DMA2_Stream2;

   hdma_tim1_ch2.Init.Channel = DMA_CHANNEL_6;

   hdma_tim1_ch2.Init.Direction = DMA_MEMORY_TO_PERIPH;

   hdma_tim1_ch2.Init.PeriphInc = DMA_PINC_DISABLE;

   hdma_tim1_ch2.Init.MemInc = DMA_MINC_ENABLE;

   hdma_tim1_ch2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

   hdma_tim1_ch2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

   hdma_tim1_ch2.Init.Mode = DMA_CIRCULAR;

   hdma_tim1_ch2.Init.Priority = DMA_PRIORITY_LOW;

   hdma_tim1_ch2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

   if (HAL_DMA_Init(&hdma_tim1_ch2) != HAL_OK)

   {

     Error_Handler();

   }

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_CC2],hdma_tim1_ch2);

   /* TIM1_CH3 Init */

   hdma_tim1_ch3.Instance = DMA2_Stream6;

   hdma_tim1_ch3.Init.Channel = DMA_CHANNEL_6;

   hdma_tim1_ch3.Init.Direction = DMA_MEMORY_TO_PERIPH;

   hdma_tim1_ch3.Init.PeriphInc = DMA_PINC_DISABLE;

   hdma_tim1_ch3.Init.MemInc = DMA_MINC_ENABLE;

   hdma_tim1_ch3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

   hdma_tim1_ch3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

   hdma_tim1_ch3.Init.Mode = DMA_CIRCULAR;

   hdma_tim1_ch3.Init.Priority = DMA_PRIORITY_LOW;

   hdma_tim1_ch3.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

   if (HAL_DMA_Init(&hdma_tim1_ch3) != HAL_OK)

   {

     Error_Handler();

   }

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_CC3],hdma_tim1_ch3);

   /* TIM1_CH4_TRIG_COM Init */

   hdma_tim1_ch4_trig_com.Instance = DMA2_Stream4;

   hdma_tim1_ch4_trig_com.Init.Channel = DMA_CHANNEL_6;

   hdma_tim1_ch4_trig_com.Init.Direction = DMA_MEMORY_TO_PERIPH;

   hdma_tim1_ch4_trig_com.Init.PeriphInc = DMA_PINC_DISABLE;

   hdma_tim1_ch4_trig_com.Init.MemInc = DMA_MINC_ENABLE;

   hdma_tim1_ch4_trig_com.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

   hdma_tim1_ch4_trig_com.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

   hdma_tim1_ch4_trig_com.Init.Mode = DMA_CIRCULAR;

   hdma_tim1_ch4_trig_com.Init.Priority = DMA_PRIORITY_LOW;

   hdma_tim1_ch4_trig_com.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

   if (HAL_DMA_Init(&hdma_tim1_ch4_trig_com) != HAL_OK)

   {

     Error_Handler();

   }

   /* Several peripheral DMA handle pointers point to the same DMA handle.

    Be aware that there is only one stream to perform all the requested DMAs. */

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_CC4],hdma_tim1_ch4_trig_com);

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_TRIGGER],hdma_tim1_ch4_trig_com);

   __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_COMMUTATION],hdma_tim1_ch4_trig_com);

 /* USER CODE BEGIN TIM1_MspInit 1 */

 /* USER CODE END TIM1_MspInit 1 */

 }

 else if(htim_pwm->Instance==TIM3)

 {

 /* USER CODE BEGIN TIM3_MspInit 0 */

 /* USER CODE END TIM3_MspInit 0 */

   /* Peripheral clock enable */

   __HAL_RCC_TIM3_CLK_ENABLE();

 /* USER CODE BEGIN TIM3_MspInit 1 */

 /* USER CODE END TIM3_MspInit 1 */

 }

}

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