2014-07-17 12:49 AM
2014-07-17 01:57 AM
>
| ((0x01 << 23) & DMA_SxCR_MBURST) //4 beat memory burst
IMO, FSMC does not support read bursts.
JW
2014-07-17 05:33 AM
I thought that might be the problem, so tried to do it with a single transfer, but that doesn't work either. Here's the modified code for configuring the DMA:
//Set the DMA CR
tempreg = DMA_Channel_4 //Select Channel 4
| DMA_MemoryBurst_Single
| DMA_PeripheralBurst_Single
| DMA_Priority_VeryHigh //Priority is very_high
| DMA_MemoryDataSize_Word //Memory data size is 32bit (word)
| DMA_PeripheralDataSize_Word //Peripheral data size is 32bit (word)
| DMA_MemoryInc_Enable //Enable Memory Increment
| DMA_PeripheralInc_Disable //Disable Peripheral Increment
| DMA_Mode_Normal //Disable Circular mode
| ((dir == WRITE_TO_CARD) ? DMA_DIR_MemoryToPeripheral : DMA_DIR_PeripheralToMemory)
| DMA_FlowCtrl_Peripheral; //Peripheral controls the flow control. (The DMA tranfer ends when the data issues end of transfer signal regardless of ndtr value)
//Bit [4..1] is for interupt mask. I don't use interrupts here
//Bit 0 is EN. I will set it after I set the FIFO CR. (FIFO CR cannot be modified when EN=1)
DMA2_Stream3->CR = tempreg;
//Set the FIFO CR
tempreg = DMA_FIFOMode_Disable; //Fifo is disabled (Direct mode is Enabled);
DMA2_Stream3->FCR = tempreg;
#endif
//Enable the DMA (When it is enabled, it starts to respond dma requests)
DMA2_Stream3->CR |= DMA_SxCR_EN;
2014-07-17 05:56 AM
NDTR? LISR?
JW2014-07-17 07:20 AM
LISR: 0x400000 (FEIF3)
NDTR: 65534 (I'm writing to SDIO, letting the peripheral control flow) DMA2_Stream3->CR 0x80354612014-07-17 09:22 PM
tries to separate
the problem
Enable
the
DMA
and stop the code execution before
the
SDIO block
write command
if
the configuration of the
DMA
is correct
you have to see
that the FS field
in the
DMA_SxFCR
register
changes from0x04
(
FIFOempty
) to0x05
(
FIFOfull)
It means that the
DMA
transfer
has
started
ok
and wait
for
SDIO
peripheral
.I guess the
firmware
checks
the status of the
SD card before
writing the block
and
configure
the block size
before start write.