DMA_DeInit implementation CCR overwrite?

[Taylor Hillegeist]

Posted on June 20, 2018 at 18:27

In the stem32f10x_dma.c the DMA_DeInit function has the following lines:

/* Disable the selected DMAy Channelx */

DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); /* Reset DMAy Channelx control register */ DMAy_Channelx->CCR = 0;

I can't quite figure out why there is a double write to the CCR register. After digging through the documents i did find a note:

Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers

(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during

the channel configuration phase.

However this note makes the code make even less sense, because the /*Reset DMAy_Channelx control register*/ action would not do anything? So is one of these lines

unnecessary? what is the actual purpose of the double write to CCR?

[Tesla DeLorean]

Posted on June 21, 2018 at 01:01

Perhaps it avoids some hazards by cleanly stopping the DMA unit, before changing all the settings? It is not a 'memory' location, as much as it is the control to some pipelined state machine.

The automotive equivalent to being at a complete stop before dragging the shifter all the way across to PARK.

[Taylor Hillegeist]

Posted on June 21, 2018 at 22:42

Well thanks for the reply, however I'm looking for a bit more than speculation. Disabling the channel would prevent other information from being edited according to the note, Its on pg 278 of the 

https://www.st.com/content/ccc/resource/technical/document/reference_manual/59/b9/ba/7f/11/af/43/d5/CD00171190.pdf/files/CD00171190.pdf/jcr:content/translations/en.CD00171190.pdf

. But this may be useful if the theory is testable, I dont know if you could tell the difference given that the time to write to the register takes almost no time, it would give the DMA very little time to adjust to any changes before being disabled. It might also be good to know who/where to find answers on this library if you have any information, that would be great. Thanks!

[Tesla DeLorean]

Posted on June 22, 2018 at 01:17

The SPL is deprecated, the F1 design is a decade old, the FAE servicing your account would probably the best point person, the IC Design Engineers don't frequent the forum, the ones on the F1 design likely 5-6 projects beyond that. There is a separate 'Online Support Ticket' system that might be worth a try.

The back-to-back write to the AHB/APB are of the order of 4-cycles. Doing things like TIM2->CNT += 8; won't advance the counter. And TIM1->SR &= ~1; induces hazards.