DMA and CPU accessing SRAM same time

[nmadhavan]

Posted on March 19, 2014 at 15:28

Hi,

I am working on a system using STM 32F107 processor(connectivity line). Because of our requirement same memory location of SRAM is accessed by both CPU and DMA. CPU is supposed to move the data from initial location A to location B(on SRAM) while DMA is supposed to update location A. But we are experiencing a duplicate data at location B. This can only happen if the DMA is not updating during CPU is moving data from A to B. What could be the reason for this? Is this due to a BUS crunch? When CPU and DMA is accessing same peripheral, DMA should get priority right? In that case we should not be getting duplicate data. Any inputs are appreciated. 

[Tesla DeLorean]

Posted on March 19, 2014 at 15:47

For any memory interaction, there is the potential for contention, when two device want to access the same region, depending if one has already started, or the priority, one will occur before the other.

I can't speak to what you're doing, but the rate a which each interacts with the memory will impact the apparent sequence of operation, and the potential for contention. Analyse the bus speeds of the memories involved, and the bandwidth of the operations.

[chen]

Posted on March 19, 2014 at 15:51

Hi

''CPU is supposed to move the data from initial location A to location B(on SRAM) while DMA is supposed to update location A. But we are experiencing a duplicate data at location B. This can only happen if the DMA is not updating during CPU is moving data from A to B.'' I do not agree with this diagnosis. It is possible for CPU to copy the same data. What triggers the CPU to do the copy/move? I am asking - what is the logic that switches between the 2? ''When CPU and DMA is accessing same peripheral, DMA should get priority right?'' No. Priority go to whichever started first.

[nmadhavan]

Posted on March 19, 2014 at 20:21

@Sung: you are right.CPU is copying same data multiple times. It is because DMA is not updating the Location A in between the transfer. Both DMA transfer rate and CPU tranfer occurs at 20 Khz but it is out of sync.(please see the attachment for better understanding)

I cannot sync them due to design requirement. CPU transfer rate is triggered at 20 khz by the receiver. The situation occurs when DMA brings in data while CPU is transferring the data. I need to move data pretty fast from location A to location B ( in between adjacent DMA transfer). If I am using DMA controller 2 for a memory to memory transfer would that be more efficient? I have seen in the documentation that it is not recommended to use DMA in circular mode and mem2mem transfer at same time. Could I work around that problem by using 2 DMA controllers? ________________ Attachments : DMAissue.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1HF&d=%2Fa%2F0X0000000bkh%2FeY9pe3ZqRFpbr8C7Kopg1ABu8PMsXfVreq_HtEAXlEw&asPdf=false

[chen]

Posted on March 20, 2014 at 10:35

Hi

''It is because DMA is not updating the Location A in between the transfer. Both DMA transfer rate and CPU tranfer occurs at 20 Khz but it is out of sync.'' '' I cannot sync them due to design requirement.'' OK, so the fundamental problem here is synchronizing the SPI transfer and the memory to memory transfer. It sounds to me like there needs to be some logic (code) controlling it. A simple : when SPI transfer completed - do memory transfer When memory transfer completed - wait for SPI transfer. Also need to think about what happens when there is a collision. ''If I am using DMA controller 2 for a memory to memory transfer would that be more efficient?'' Yes. '' I have seen in the documentation that it is not recommended to use DMA in circular mode and mem2mem transfer at same time. Could I work around that problem by using 2 DMA controllers?'' I am not familiar with that in the document. I expect it is saying that if you do DMA location A to B then do DMA B back to A - they cannot guarantee it will work properly. In any case, you are not doing that. You are doing DMA Z to A with one DMA channel then you are doing DMA A to B with another channel.

[Tesla DeLorean]

Posted on March 20, 2014 at 12:24

Ok, so why do you need two DMA operations, could you not just make the first buffer deeper? Or twice as big, and use HT/TC interrupts to trigger it?

[jpeacock2399]

Posted on March 20, 2014 at 14:51

How do you determine when the DMA transfer is complete?  This sounds like a synchronization problem with the DMA controller.  Look at the HT half transfer flag on the DMA channel.  You can use it to determine when the DMA buffer has data, at which point you empty that part of the buffer while DMA is filling the other half.  At the TC event you can trnasfer the second half while the first part of the buffer is active.

The F2 and F4 series have several enhancements to reduce bus contention between DMA and CPU, including a bus matrix for overlapped access and a FIFO for burst mode DMA.  You might want to look at those parts if you have a bus contention problem.  I use an STM32F405 with a DMA transfer to non-cached SRAM2 and 4 word (16 byte) burst mode DMA, while operating out of CCM and cached SRAM1, no bus contentions so the memory operations overlap.  DMA is essentially a free operation in that no CPU time is lost.   Jack Peacock

[nmadhavan]

Posted on March 20, 2014 at 19:16

@sung: I am currently not using two DMAs to transfer data. I am just using one DMA  which is to transfer data from peripheral to SRAM location A and from SRAM location A to SRAM location B is done by a ''while loop'' no DMA involved. I was wondering would it be more efficient to use two DMAs. Like you said there should be some logic to start the ''while'' loop/DMA to prevent same time memory accessing which I kind of lacks. I currently take the data as soon as the trigger comes from the receiver and stores in a 2D array. Since I dont know when the trigger happens, I have to same some other location. I think like, clive said,i have to try half transfer interrupt of DMA to start moving items from first half and FT interrupt to do the later half. Thanks all. I am still wondering DMA better than ''while'' loop if I have a logic which stops memory overlapping?

Thank you all for great support...